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FUSB307BMPX

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57
FUSB307B
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7
I
2
C Interface
The FUSB307B includes a full I
2
C slave controller. The
I2C slave fully complies with the I2C specification version
6 requirements. This block is designed for fast mode plus
signals.
Examples of an I
2
C write and read sequence are shown in
Figure 7 and Figure 8 respectively.
S
WR A
AA A A
A P
NOTE: Single Byte read is initiated by Master with P immediately following first data byte.
8bits 8bits 8bits
Write Data K+2
Slave Address
Register Address K Write Data Write Data K+1 Write Data K+N−1
S WR A A S RD A A A NA P
Register address to Read specified
8bits
NOTE: If Register is not specified Master will begin read from current register. In this case only sequence showing in Red
bracket is needed.
Single or multi byte read executed from current register location
(Single Byte read is initiated by Master with NA immediately following first data byte)
Read Data K+1 Read Data K+N−1
8bits 8bits 8bits
Slave Address
Register Address K Read Data KSlave Address
From Master to Slave S Start Condition NA NOT Acknowledge (SDA High) RD Read =1
From Slave to Master A Acknowledge (SDA Low) WR Write = 0 P
Stop Condition
Figure 6. I2C Write Example
Figure 7. I2C Read Example
I
2
C Address Selection
I2C Slave addresses can be changed by configuring the
I2C_ADDR_GPO input on power up with a pull−up or
pull−down resistor and routing the SCL and SDA lines
according to Table 3.
Interrupt Operation
The INT_N pin is an active low, open drain output which
indicates to the host processor that an interrupt has occurred
in the FUSB307B which needs attention. The INT_N pin is
asserted after power−up or device reset RESET.SW_RES
set to 1b (due to ALERTL.I_PORT_PWR and
PWRSTAT.TCPC_INIT).
When an interruptible event occurs, INT_N is driven low
and is high−Z again when the processor clears the interrupt
by writing a 1 to the corresponding interrupt bit position.
Writing a 0 to an interrupt bit has no effect.
A processor firmware has additional control of INT_N
through individual event mask bits which can be set or
cleared to enable or disable INT_N from being driven low
when each event occurs.
Table 3. I
2
C ADDRESSES
I2C_ADDR
SCLx/SDAx
Slave Address
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 SCL1/SDA1 1 0 1 0 0 0 0 R/W
1 SCL1/SDA1 1 0 1 0 0 0 1 R/W
0 SCL2/SDA2 1 0 1 0 0 1 0 R/W
1 SCL2/SDA2 1 0 1 0 0 1 1 R/W
I
2
C Idle Mode
Entering I
2
C Idle Mode
The FUSB307B does not need to enter I
2
C Idle Mode in
order to save power. Entering this mode has no effect on I
2
C
function. The FUSB307B can enter idle mode if 0xFF is
written to the COMMAND register. Once in Idle mode, the
FUSB307B will not set the PWRSTAT.TCPC_INIT to one.
Exiting I
2
C Idle Mode
The FUSB307B will exit I
2
C Idle mode when any I
2
C
communication is addressed to the slave. The
ALERTL.I_PRT_PWR interrupt will be set and no
PWRSTAT bits will be set.
The device’s I
2
C block is always on without power
penalties.
FUSB307B
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8
VCONN Control
The FUSB307B integrates a CCx to VCONN switch with
programmable OCP capability via the VCONN_OCP
register. If PWRCTRL.VCONN_PWR is set to 0, the
standard VCONN current limit is used (210.5 mA). If
PWRCTRL.VCONN_PWR is set to 1, the programmable
VCONN_OCP is used.
The VCONN switch can be enabled via the PWRCTRL
register bits EN_VCONN and TCPC_CTRL.ORIENT bits
(for CC1/2 selection).
A VCONN valid voltage is monitored and reported on
PWRSTAT.VCONN_VAL. The valid voltage threshold is
fixed at 2.4 V.
Debug Accessory Support
The FUSB307B implements autonomous detection of
Source and Sink debug accessories. A debug accessory
detection is indicated via a standard output. The FUSB307B
powers on looking for a debug accessories without
processor intervention.
If debug accessory detection is not wanted, the processor can
write TCPC_CTRL.DEBUG_ACC_CTRL = 1b.
Type−C Manual Mode Detection
The CC pull up (Rp) or pull down (Rd) resistors and DRP
toggle are setup via the ROLECTRL register.If a TCPM
wishes to control Rp/Rd directly, it can write
ROLECTRL.DRP = 0b and the desired ROLECTRL bits
[3:0] (CC1/CC2).
The FUSB307B can autonomously toggle the Rp/Rd by
setting ROLECTRL.DRP = 1b and the starting value of
Rp/Rd in ROLECTRL.bits [3:0]. DRP toggling starts by
writing to the COMMAND register
If ROLECTRL.DRP = 1b, the only allowed values for
CC1/CC2 in ROLECTRL bits [3:0] are Rp/Rp or Rd/Rd.
When ROLECTRL bits 3:0 are set to Open and
ROLECTRL.DRP = 0b, the PHY and CC comparators are
powered down.
The FUSB307B updates the CCSTAT register on a
Connect, Disconnect, a change in ROLECTRL.DRP or a
change (tTCPCFilter debounced) on the CC1 or CC2 wire.
The TCPM reads CCSTAT upon detecting an interrupt
and seeing the ALERTL.I_CCSTAT = 1. The FUSB307B
indicates the DRP status, the DRP result, and the current CC
status in this register.
The FUSB307B will set CCSTAT.LOOK4CON = 0b
when it has stopped toggling as a DRP.
The TCPM reads the CCSTAT.LOOK4CON to determine
if the FUSB307B is toggling Rp/Rd when operating as a
DRP, it then reads CCSTAT.CON_RES to determine if the
FUSB307B is presenting an Rp or Rd and read the
CCSTAT.CC1_STAT and CCSTAT.CC2_STAT to
determine the CC1 and CC2 states.
The FUSB307B debounces the CC lines for tTCPCfilter
before reporting the status on CCSTAT. The TCPM must
complete the debounce as defined in Type−C Specification.
FUSB307B
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9
Figure 8. DRP Initialization and Connection Detection
Set FUSB305B to DRP
Write:
ROLECTRL.DRP = 1b
ROLECTRL.CC2 = 01b or 10b
ROLECTRL.CC1 = 01b or10b
ROLECTRL.CC1 = ROLECTRL.CC2
PWRCTRL.AUTO_DISCH = 0b
COMMAND.LOOK4CON
No Connection
Monitor for
Alert
ALERT.CCSTAT = 1b?
DRP Toggling
Set CCSTAT.LOOK4CON = 1b
DrpToggleFlag = 1b
Start DRP Toggling
Monitor for a Connection
Potential Connect As Source
Either CC = Src.Rd or Both CC = Src.Ra
for > tTCPCFilter
Potential Connect As Sink
Either CC != Snk.Open
for > tTCPCFilter
Set Source Status
CCSTAT.LOOK4CON = 0b
CCSTAT.CON_RES = 0b
Stop Toggling Rp/Rd
Apply Rp
Set Sink Status
CCSTAT.LOOK4CON = 0b
CCSTAT.CON_RES = 1b
Stop Toggling Rp/Rd
Apply Rd
Interrupt
Set
ALERT.CCSTAT = 1b
Read ALERT
Service other
ALERTS
Read CCSTAT
CCSTAT.LOOK4CON = 0b?
Debounce CC Status
Read CCSTAT and debounce for
tCCDebounce
Determine CC & VCONN
Write:
ROLECTRL.CC1 & CC2 per decision
Set PWRCTRL.AUTO_DISCH
TCPC_CTRL.ORIENT
PWRCTRL.EN_VCONN
Clear ALERT.CCSTAT
Connection Established
Monitor for ALERT
Monitor for a disconnect
No
Yes
Yes
No
FUSB307B
TCPM
Connection
Enable VBUS and VCONN
Write COMMAND to Source/Sink Vbus per decision
Check PWRSTAT.VBUS_VAL = 1b
Check PWRSTAT.VCONN_VAL = 1b
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57

FUSB307BMPX

Mfr. #:
Buy FUSB307BMPX
Manufacturer:
ON Semiconductor
Description:
USB Interface IC USB-C TCPC PORT CONT
Lifecycle:
New from this manufacturer.
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