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FUSB307BMPX

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57
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Table 50. STD_OUT_CAP
Address: 29h
Reset Value: FUSB307B: 0x41
Type: Read
Bit #
Name R/W/C Size (Bits) Standard Outputs Capabilities Description
7 Reserved R 1 Reserved: 00b
6 DEBUG_ACC R 1 0b: Debug Accessory Indicator Not Present
1b: Debug Accessory Indicator Present
5 VBUS_MON R 1 0b: VBUS Present Monitor Not Present
4 AUDIO_ACC R 1 0b: Audio Adapter Accessory Indicator Not Present
3 ACTIVE_CABLE R 1 0b: Active Cable Indicator not Present
2 MUX_CTRL R 1 0b: Mux Control Not Present
1 CON_PRESENT R 1 0b: Connection Present indicator not implemented
0 ORIENT R 1 1b: Connector Orientation Present
Table 51. MSGHEADR
Address: 2Eh
Reset Value: 0x02 for FUSB307B
Type: Read/Write
Bit #
Name R/W/C Size (Bits) Message Header Info Description
7:5 Reserved R 3 Reserved: 000b
4 CBL_PLUG R/W 1 Cable Plug
0b: Message originated from Source, Sink, or DRP
1b: Message originated from a Cable Plug
3 DATA_ROLE R/W 1 Data Role
0b: SINK
1b: SOURCE
2:1 USBPD_REV R/W 2 USB−PD Specification Revision
00b: Revision 1.0
01b: Revision 2.0
10b – 11b: Reserved
0 POWER_ROLE R/W 1 Power Role
0b: Sink
1b: Source
Table 52. RXDETECT
RXDETECT enables the types of messages and/or signaling to be detected. SOP* enabling also turns on auto−GoodCRC response.
This register is reset when: A Hard Reset is received or sent; after the GoodCRC transmission due to RxOneMore; on a disconnect
detection; SW_RST or POR.
Address: 2Fh
Reset Value: 0x00
Type: Read/Write
Bit #
Name R/W/C Size (Bits) Receive Detect Description (Note 35)
7
Reserved R 1
Reserved: 0b
6
EN_CABLE_RST R 1
0b: Do not detect Cable Reset signaling
5
EN_HRD_RST R/W 1
0b: Do not detect Hard Reset signaling (default)
1b: Detect Hard Reset signaling
4
EN_SOP2_DBG R/W 1
0b: Do not detect SOP_DBG” message (default)
1b: Detect SOP_DBG” message
3
EN_SOP1_DBG R/W 1
0b: Do not detect SOP_DBG’ message (default)
1b: Detect SOP_DBG’ message
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Table 52. RXDETECT (continued)
RXDETECT enables the types of messages and/or signaling to be detected. SOP* enabling also turns on auto−GoodCRC response.
This register is reset when: A Hard Reset is received or sent; after the GoodCRC transmission due to RxOneMore; on a disconnect
detection; SW_RST or POR.
Address: 2Fh
Reset Value: 0x00
Type: Read/Write
Bit #
Receive Detect Description (Note 35)Size (Bits)R/W/CName
2
EN_SOP2 R/W 1
0b: Do not detect SOP” message (default)
1b: Detect SOP” message
1
EN_SOP1 R/W 1
0b: Do not detect SOP’ message (default)
1b: Detect SOP’ message
0
EN_SOP R/W 1
0b: Do not detect SOP message (default)
1b: Detect SOP message
35.Writing all 0s to this register disables PD.
Table 53. RXBYTECNT
Address: 30h
Reset Value: 0x00
Type: Read
Bit #
Name R/W/C Size (Bits) Received Byte Count Description
7:0 RXBYTECNT R 8 Number of Bytes Received. This is the number of bytes in RXDATA
plus 3 (RXSTAT and RXHEADL, H)
Table 54. RXSTAT
This register indicates the status of the received SOP* message in RXHEADL,RXHEADH, and RXDATA registers.
Address: 31h
Reset Value: 0x00
Type: Read
Bit #
Name R/W/C Size (Bits) Receive Status Description
7:3 Reserved R 5 Reserved: 00000b
2:0
RXSOP R 3
Received SOP
000b: Received SOP
001b: Received SOP’
010b: Received SOP’’
011b: Received SOP’_DBG
100b: Received SOP”_DBG
110b: Received Cable Reset
All others are reserved.
Table 55. RXHEADL
Received Header Low byte is stored here. Expected GoodCRC messages are not stored.
Address: 32h
Reset Value: 0x00
Type: Read
Bit #
Name R/W/C Size (Bits) Receive Header Low Description
7:0 RXHEADL R 8 Rx Header Data Low
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Table 56. RXHEADH
Received Header High byte is stored here. Expected GoodCRC messages are not stored.
Address: 33h
Reset Value: 0x00
Type: Read
Bit #
Name R/W/C Size (Bits) Receive Header High Description
7:0 RXHEADH R 8 Rx Header Data High
Table 57. RXDATA
Address: 34h−4Fh
Reset Value: 0x00
Type: Read
Byte #
Name R/W/C Size (Bits) Receive Payload Description
27:0 RXDATA0..27 R 8 Rx Payload
Table 58. TRANSMIT
Writing this register will start a PD transmission. If Cable Reset, Hard Reset or BIST Carrier Mode 2 is written, RETRY_CNT is ignored
and signaling is not retried.
Address: 50h
Reset Value: 0x00
Type: Read/Write
Bit #
Name R/W/C Size (Bits) Transmit Description
7:6 Reserved R 2 Reserved: 00b
5:4 RETRY_CNT R/W 2 Retry Counter
00b: No message retry is required
01b: Automatically retry message transmission once
10b: Automatically retry message transmission twice
11b: Automatically retry message transmission three times
3 Reserved R 1 Reserved: 0b
2:0 TXSOP R/W 3 Transmit SOP Message
000b: Transmit SOP
001b: Transmit SOP’
010b: Transmit SOP’’
011b: Transmit SOP_DBG’
100b: Transmit SOP_DBG”
101b: Transmit Hard Reset
110b: Transmit Cable Reset
111b: Transmit BIST Carrier Mode 2
(Enabled for tBISTContMode)
Table 59. TXBYTECNT
Address: 51h
Reset Value: 0x00
Type: Read/Write
Bit #
Name R/W/C Size (Bits) Transmit Byte Count Description
7:0 TXBYTECNT R/W 8 Number of bytes to be transmitted
Table 60. TXHEADL
Address: 52h
Reset Value: 0x00
Type: Read/Write
Bit #
Name R/W/C Size (Bits) Transmit Header Low Description
7:0 TXHEADL R/W 8 Transmit Header Low
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57

FUSB307BMPX

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Buy FUSB307BMPX
Manufacturer:
ON Semiconductor
Description:
USB Interface IC USB-C TCPC PORT CONT
Lifecycle:
New from this manufacturer.
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