Data Sheet ADuM1100
Rev. K | Page 9 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
Pulse Width Distortion, |t
PLH
− t
PHL
|
5
PWD
5 V/3 V Operation 0.5 2 ns C
L
= 15 pF, CMOS signal levels
3 V/5 V Operation 0.5 3 ns C
L
= 15 pF, CMOS signal levels
Change in Pulse Width Distortion vs.
Temperature
6
5 V/3 V Operation 3 ps/°C C
L
= 15 pF, CMOS signal levels
3 V/5 V Operation 10 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew (Equal
Temperature)
5, 7
t
PSK1
5 V/3 V Operation 12 ns C
L
= 15 pF, CMOS signal levels
3 V/5 V Operation 15 ns C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew (Equal
Temperature, Supplies)
5, 7
t
PSK2
5 V/3 V Operation 9 ns C
L
= 15 pF, CMOS signal levels
3 V/5 V Operation 12 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
, t
F
3 ns C
L
= 15 pF, CMOS signal levels
Common-Mode Transient Immunity at
Logic Low/High Output
8
|CM
L
|,
|CM
H
|
25 35 kV/µs V
I
= 0 V or V
DD1
, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate f
r
5 V/3 V Operation 1.2 Mbps
3 V/5 V Operation 1.1 Mbps
Input Dynamic Supply Current
9
C
PD1
5 V/3 V Operation 0.09 mA/Mbps
3 V/5 V Operation 0.08 mA/Mbps
Output Dynamic Supply Current
9
C
PD2
5 V/3 V Operation 0.04 mA/Mbps
3 V/5 V Operation 0.02 mA/Mbps
1
Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See
the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
is measured from the 50% level of the falling edge of the V
I
signal to the 50% level of the falling edge of the V
O
signal. t
PLH
is measured from the 50% level of the
rising edge of the V
I
signal to the 50% level of the rising edge of the V
O
signal.
5
Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width
distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the
impact of given input rise/fall times on these parameters.
6
Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.
7
t
PSK1
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature and output load within the
recommended operating conditions. t
PSK2
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
8
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range
over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on
supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given
data rate and output load.
