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ADUM1100UR-RL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
ADuM1100 Data Sheet
Rev. K | Page 6 of 20
ELECTRICAL SPECIFICATIONS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ V
DD1
≤ 3.6 V, 3.0 V ≤ V
DD2
≤ 3.6 V. All minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 3.3 V.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current I
DD1 (Q)
0.1 0.3 mA V
I
= 0 V or V
DD1
Output Supply Current I
DD2 (Q)
0.005 0.04 mA V
I
= 0 V or V
DD1
Input Supply Current (25 Mbps)
(See Figure 5)
I
DD1 (25)
2.0 2.8 mA 12.5 MHz logic signal frequency
Output Supply Current
1
(25 Mbps)
(See Figure 6)
I
DD2 (25)
0.3 0.7 mA 12.5 MHz logic signal frequency
Input Supply Current (50 Mbps)
(See Figure 5)
I
DD1 (50)
4.0 6.0 mA 25 MHz logic signal frequency,
ADuM1100BR/ADuM1100UR only
Output Supply Current
1
(50 Mbps)
(See Figure 6)
I
DD2 (50)
1.2 1.6 mA 25 MHz logic signal frequency,
ADuM1100BR/ADuM1100UR only
Input Current I
I
−10 +0.01 +10 µA 0 V ≤ V
IN
≤ V
DD1
Logic High Output Voltage V
OH
V
DD2
− 0.1 3.3 V I
O
= −20 μA, V
I
= V
IH
V
DD2
− 0.5 3.0 V I
O
= −2.5 mA, V
I
= V
IH
Logic Low Output Voltage V
OL
0.0 0.1 V I
O
= 20 μA, V
I
= V
IL
0.04 0.1 V I
O
= 400 μA, V
I
= V
IL
0.3 0.4 V I
O
= 2.5 mA, V
I
= V
IL
SWITCHING SPECIFICATIONS
For ADuM1100AR
Minimum Pulse Width
2
PW 40 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
25 Mbps C
L
= 15 pF, CMOS signal levels
For ADuM1100BR/ADuM1100UR
Minimum Pulse Width
2
PW 10 20 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
50 100 Mbps C
L
= 15 pF, CMOS signal levels
For All Grades
Propagation Delay Time to Logic Low
Output
4, 5
(See Figure 8)
t
PHL
14.5 28 ns C
L
= 15 pF, CMOS signal levels
Propagation Delay Time to Logic
High Output
4, 5
(See Figure 8)
t
PLH
15.0 28 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion |t
PLH
− t
PHL
|
5
PWD
0.5
3
ns
C
L
= 15 pF, CMOS signal levels
Change vs. Temperature
6
10 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
(Equal Temperature)
5, 7
t
PSK1
15 ns C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
(Equal Temperature, Supplies)
5, 7
t
PSK2
12 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time
t
R
, t
F
3
ns
C
L
= 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic Low/High Output
8
|CM
L
|,
|CM
H
|
25 35 kV/µs V
I
= 0 V or V
DD1
, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate f
r
1.1 Mbps
Input Dynamic Supply Current
9
I
DDI (D)
0.08 mA/Mbps
Output Dynamic Supply Current
9
I
DDO (D)
0.04 mA/Mbps
Data Sheet ADuM1100
Rev. K | Page 7 of 20
1
Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See
the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
is measured from the 50% level of the falling edge of the V
I
signal to the 50% level of the falling edge of the V
O
signal. t
PLH
is measured from the 50% level of the
rising edge of the V
I
signal to the 50% level of the rising edge of the V
O
signal.
5
Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width
distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the
impact of given input rise/fall times on these parameters.
6
Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.
7
t
PSK1
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature and output load within the
recommended operating conditions. t
PSK2
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
8
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range
over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on
supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given
data rate and output load.
ADuM1100 Data Sheet
Rev. K | Page 8 of 20
ELECTRICAL SPECIFICATIONS—MIXED 5 V/3 V OR 3 V/5 V OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V ≤ V
DD1
≤ 5.5 V, 3.0 V ≤ V
DD2
≤ 3.6 V. 3 V/5 V operation:
3.0 V ≤ V
DD1
≤ 3.6 V, 4.5 V ≤ V
DD2
≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= 3.3 V, V
DD2
= 5 V or V
DD1
= 5 V, V
DD2
= 3.3 V.
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent I
DDI (Q)
5 V/3 V Operation 0.3 0.8 mA
3 V/5 V Operation 0.1 0.3 mA
Output Supply Current, Quiescent I
DDO (Q)
5 V/3 V Operation 0.005 0.04 mA
3 V/5 V Operation 0.01 0.06 mA
Input Supply Current, 25 Mbps I
DDI (25)
5 V/3 V Operation 2.2 3.5 mA 12.5 MHz logic signal frequency
3 V/5 V Operation
2.0
2.8
12.5 MHz logic signal frequency
Output Supply Current
1
, 25 Mbps I
DDO (25)
5 V/3 V Operation 0.3 0.7 mA 12.5 MHz logic signal frequency
3 V/5 V Operation 0.5 1.0 mA 12.5 MHz logic signal frequency
Input Supply Current, 50 Mbps I
DDI (50)
5 V/3 V Operation 4.5 7.0 mA 25 MHz logic signal frequency
3 V/5 V Operation 4.0 6.0 mA 25 MHz logic signal frequency
Output Supply Current
1
, 50 Mbps I
DDO (50)
5 V/3 V Operation 1.2 1.6 mA 25 MHz logic signal frequency
3 V/5 V Operation 1.0 1.5 mA 25 MHz logic signal frequency
Input Currents I
IA
−10 +0.01 +10 μA 0 V ≤ V
IA
, V
IB
, V
IC
, V
ID
≤ V
DD1
or V
DD2
Logic High Output Voltage V
OH
V
DD2
− 0.1 3.3 V I
O
= −20 μA, V
I
= V
IH
5 V/3 V Operation V
DD2
− 0.5 3.0 V I
O
= −2.5 mA, V
I
= V
IH
Logic Low Output Voltage V
OL
0.0 0.1 V I
O
= 20 μA, V
I
= V
IL
5 V/3 V Operation 0.04 0.1 V I
O
= 400 μA, V
I
= V
IL
0.3 0.4 V I
O
= 2.5 mA, V
I
= V
IL
Logic High Output Voltage V
OH
V
DD2
− 0.1 5.0 V I
O
= −20 μA, V
I
= V
IH
3 V/5 V Operation
V
DD2
− 0.8
4.6
I
O
= −4 mA, V
I
= V
IH
Logic Low Output Voltage V
OL
0.0 0.1 V I
O
= 20 μA, V
I
= V
IL
3 V/5 V Operation 0.03 0.1 V I
O
= 400 μA, V
I
= V
IL
0.3 0.8 V I
O
= 4 mA, V
I
= V
IL
SWITCHING SPECIFICATIONS
For ADuM1100AR
Minimum Pulse Width
2
PW 40 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
25 Mbps C
L
= 15 pF, CMOS signal levels
For ADuM1100BR/ADuM1100UR
Minimum Pulse Width
2
PW 20 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
50 Mbps C
L
= 15 pF, CMOS signal levels
For All Grades
Propagation Delay Time to Logic
Low/High Output
4, 5
t
PHL
, t
PLH
5 V/3 V Operation (See Figure 9) 13 21 ns C
L
= 15 pF, CMOS signal levels
3 V/5 V Operation (See Figure 10) 16 26 ns C
L
= 15 pF, CMOS signal levels
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

ADUM1100UR-RL7

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