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ACPL-312U-500E

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
13
Applications Information
Eliminating Negative IGBT Gate Drive ACPL-312U
To keep the IGBT rmly o, the ACPL-312U has a very
low maximum V
OL
specication of 0.5 V. The ACPL-312U
realizes this very low V
OL
by using a DMOS transistor
with 1 Ω (typical) on resistance in its pull down circuit.
When the ACPL-312U is in the low state, the IGBT gate is
shorted to the emitter by Rg + 1 Ω. Minimizing Rg and
the lead inductance from the ACPL-312U to the IGBT gate
and emitter (possibly by mounting the ACPL-312U on a
small PC board directly above the IGBT) can eliminate the
need for negative IGBT gate drive in many applications
as shown in Figure 25. Care should be taken with such
a PC board design to avoid routing the IGBT collector or
emitter traces close to the ACPL-312U input as this can
result in unwanted coupling of transient signals into the
ACPL-312U and degrade performance. (If the IGBT drain
must be routed near the ACPL-312U input, then the LED
should be reverse-biased when in the o state, to prevent
the transient signals coupled from the IGBT drain from
turning on the ACPL-312U).
Figure 25. Recommended LED drive and application circuit.
Selecting the Gate Resistor (Rg) to Minimize IGBT Switching
Losses.
Step 1: Calculate Rg Minimum from the I
OL
Peak Speci-
cation. The IGBT and Rg in Figure 26 can be analyzed as
a simple RC circuit with a voltage supplied by the ACPL-
312U.
The V
OL
value of 2.5V in the previous equation is a conser-
vative value of VOL at the peak current of 2.5A (see Figure
6). At lower Rg values the voltage supplied by the ACPL-
312U is not an ideal voltage step. This results in lower peak
currents (more margin) than predicted by this analysis.
When negative gate drive is not used VEE in the previous
equation is equal to zero volts.
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF
V
CC
= 18 V
1
3
+
–
2
4
8
6
7
5
270 Ω
ACPL-312U
+5 V
CONTROL
INPUT
Rg
Q1
Q2
CMOS
DRIVER
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF
V
CC
= 15 V
1
3
+
–
2
4
8
6
7
5
Rg
Q1
Q2
V
EE
= -5 V
–
+
270 Ω
+5 V
CONTROL
INPUT
CMOS
DRIVER
Figure 26. ACPL-312U typical application circuit with negative IGBT gate drive.
I
OLPEAK
R
g
(V
CC
− V
EE
− V
OL
)
≥
I
OLPEAK
(V
CC
− V
EE
− 2.5V )
=
2.5 A
(15 + 5 − 2.5V)
=
R
g
= 7ohm
14
Step 2: Check the ACPL-312U Power Dissipation and Increase
Rg if Necessary.
The ACPL-312U total power dissipation (P
T
) is equal to the
sum of the emitter power (P
E
) and the output power (P
O
):
P
T
= P
E
+ P
O
P
E
= I
F
.V
F
.Duty Cycle
P
O
= P
O(BIAS)
+ P
O (SWITCHING)
= I
CC
.(V
CC
- V
EE
) + E
SW
(R
G
, Q
G
).f
For the circuit in Figure 26 with I
F
(worst case) = 16 mA,
Rg = 8 Ω, Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz:
P
E
= 16mA . 1.95V . 0.8 = 24.96mW
P
O
= 5mA .20V + 5.2μJ .20kHz
= 100mW + 104mW
= 204mW
Step 3: Comparing the calculated power dissipation with the
absolute maximum values for the ACPL-312U:
P
O
= 204mW < 370mW (abs. max.)OK
P
T
= 24.96mW + 204mW
= 228.96mW < 400mW (abs. max.) OK
Therefore, the power dissipation absolute maximum
rating has not been exceeded for the example.
Esw – ENERGY PER SWITCHING CYCLE – µJ
0
0
Rg – GATE RESISTANCE –
50
6
10
14
20
4
30 40
12
Qg = 100 nC
Qg = 500 nC
Qg = 1000 nC
10
8
2
V
CC
= 19 V
V
EE
= -9 V
Ω
Figure 27. Energy dissipated in the ACPL-312U for each IGBT switching cycle.
Thermal Model
The steady state thermal model for the ACPL-312U is
shown in Figure 28. The thermal resistance values given
in this model can be used to calculate the temperatures
at each node for a given operating condition. As shown
by the model, all heat generated ows through q
CA
which
raises the case temperature TC accordingly. The value of
q
CA
depends on the conditions of the board design and is,
therefore, determined by the designer. The value of q
CA
=
83°C/W was obtained from thermal measurements using
a 2.5 x 2.5 inch PC board, with small traces (no ground
plane), a single ACPL-312U soldered into the center of
the board and still air. The absolute maximum power dis-
sipation de-rating specications assume a q
CA
value of
83°C/W. From the thermal mode in Figure 28 the LED and
detector IC junction temperatures can be expressed as:
Inserting the values for q
LC
and q
DC
shown in Figure 28
gives:
T
JE
= P
E
.(256°C/W + q
CA
) + P
D
.(57°C/W + q
CA
) + T
A
T
JD
= P
E
.(57°C/W + q
CA
) + P
D
.(111°C/W + q
CA
) + T
A
For example, given P
E
= 30 mW, P
O
= 230 mW, T
A
= 100°C
and q
CA
= 83°C/W:
T
JE
= P
E
.339°C/W + P
D
.140°C/W + T
A
= 30 mW.339°C/W + 230 mW .140°C/W + 100°C
= 142°C
T
JD
= P
E
.140°C/W + P
D
.194°C/W + T
A
= 30 mW.140°C/W + 230 mW.194°C/W + 100°C
= 149°C
T
JE
and T
JD
should be limited to 150°C based on the board
layout and part placement (q
CA
) specic to the applica-
tion.
T
JE
= P
E
=(q
LC
|| q
LC +
q
DC
) + q
CA
)
+ P
D
. (----------- + q
CA
) + T
A
T
JD
= P
E
(----------- + q
CA
)
+P
D
. (q
DC
|| q
LD +
q
LC
) + q
CA
) + T
A
q
LC *
q
DC
q
LC +
q
DC +
q
LD
q
LC
.
q
DC
q
LC +
q
DC +
q
LD
T
JE
= LED junction temperature
T
JD
= detector IC junction temeperature
T
C
= case temperature measured at the ce nter of the package bottom
LC
= LED-to-case thermal resistance
LD
= LED-to-detector thermal resistance
DC
= detector-to-case thermal resistance
CA
= case-to-ambient thermal resistance
*
CA
will depend on the board design and the placement of the part.
LD
= 442°C/W
T
JE
T
JD
LC
= 467°C/W
DC
= 126°C/W
CA
= 83°C/W *
T
C
T
A
θ
θ
θ
θ
θ
θ
θ
θ
θ
Figure 28. Thermal model.
15
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
C
LEDO1
C
LEDO2
LED Drive Circuit Considerations for Ultra High CMR Perfor-
mance.
Without a detector shield, the dominant cause of op-
tocoupler CMR failure is capacitive coupling from the
input side of the optocoupler, through the package, to
the detector IC as shown in Figure 29. The ACPL-312U
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts the
capacitively coupled current away from the sensitive IC
circuitry. However, this shield does not eliminate the ca-
pacitive coupling between the LED and optocoupler pins
5-8 as shown in Figure 30. This capacitive coupling causes
perturbations in the LED current during common mode
transients and becomes the major source of CMR failures
for a shielded optocoupler. The main design objective of
a high CMR LED drive circuit becomes keeping the LED in
the proper state (on or o) during common mode tran-
sients. For example, the recommended application circuit
(Figure 25), can achieve 25 kV/μs CMR while minimizing
component complexity. Techniques to keep the LED in the
proper state are discussed in the next two sections.
Figure 29. Optocoupler input to output
capacitance model for unshielded opto-
couplers.
Figure 30. Optocoupler input to output
capacitance model for shielded opto-
couplers.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
C
LEDO1
C
LEDO2
CMR with the LED On (CMRH).
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriv-
ing the LED current beyond the input threshold so that
it is not pulled below the threshold during a transient.
A minimum LED current of 10 mA provides adequate
margin over the maximum IFLH of 5 mA to achieve 25 kV/
μs CMR. CMR with the LED O (CMRL). A high CMR LED
drive circuit must keep the LED o (V
F
≤ V
F(OFF)
) during
common mode transients. For example, during a -dV
cm
/dt
transient in Figure 31, the current owing through C
LEDP
also ows through the R
SAT
and V
SAT
of the logic gate. As
long as the low state voltage developed across the logic
gate is less than V
F(OFF)
, the LED will remain o and no
common mode failure will occur. The open collector drive
circuit, shown in Figure 32, cannot keep the LED o during
a +dV
cm
/dt transient, since all the current owing through
C
LEDN
must be supplied by the LED, and it is not recom-
mended for applications requiring ultra high CMRL per-
formance. Figure 33 is an alternative drive circuit which,
like the recommended application circuit (Figure 25), does
achieve ultra high CMR performance by shunting the LED
in the o state.
Rg
1
3
V
SAT
2
4
8
6
7
5
+
V
CM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dV
CM
/dt.
+5 V
+
–
V
CC
= 18 V
• • •
• • •
0.1
µF
+
–
–
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1
I
LEDN
Figure 31. Equivalent circuit for gure 25 during common mode transient.
Figure 33. Recommended LED drive circuit for ultra-high CMR.
Rg
1
3
V
SAT
2
4
8
6
7
5
+
V
CM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dV
CM
/dt.
+5 V
+
–
V
CC
= 18 V
• • •
• • •
0.1
µF
+
–
–
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1
I
LEDN
Figure 32. Not recommended open collector drive
circuit.
Rg
1
3
V
SAT
2
4
8
6
7
5
+
V
CM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dV
CM
/dt.
+5 V
+
–
V
CC
= 18 V
• • •
• • •
0.1
µF
+
–
–
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1
I
LEDN
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

ACPL-312U-500E

Mfr. #:
Buy ACPL-312U-500E
Manufacturer:
Broadcom / Avago
Description:
Logic Output Optocouplers Gate Drive Opto
Lifecycle:
New from this manufacturer.
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