16
t
PHL MAX
t
PLH MIN
PDD* MAX = (t
PHL
-
t
PLH
)
MAX
= t
PHL MAX
-
t
PLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT 1
I
LED2
V
OUT 2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
t
PLH
MIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
PHL MAX
-
t
PHL MIN
) + (t
PLH MAX
-
t
PLH MIN
)
= (t
PHL MAX
-
t
PLH MIN
) – (t
PHL MIN
-
t
PLH MAX
)
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT 1
I
LED2
V
OUT 2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
t
PHL MIN
t
PHL MAX
t
PLH MAX
PDD* MAX
(t
PHL-
t
PLH
)
MAX
Under Voltage Lockout Feature.
The ACPL-312U contains an under voltage lockout (UVLO)
feature that is designed to protect the IGBT under fault
conditions which cause the ACPL-312U supply voltage
(equivalent to the fully-charged IGBT gate voltage) to
drop below a level necessary to keep the IGBT in a low re-
sistance state. When the ACPL-312U output is in the high
state and the supply voltage drops below the ACPL-312U
V
UVLO
– threshold (9.5 < V
UVLO
– < 12.0) the optocoupler
output will go into the low state with a typical delay, UVLO
Turn O Delay, of 0.6 μs. When the ACPL-312U output is
in the low state and the supply voltage rises above the
ACPL-312U V
UVLO+
threshold (11.0 < V
UVLO+
< 13.5) the
optocoupler output will go into the high state (assumes
LED is “ON”) with a typical delay, UVLO Turn On Delay of
0.8 μs.
Dead Time and Propagation Delay Specications
The ACPL-312U includes a Propagation Delay Dierence
(PDD) specication intended to help designers minimize
“dead time” in their power inverter designs. Dead time
is the time period during which both the high and low
side power transistors (Q1 and Q2 in Figure 25) are o.
Any overlap in Q1 and Q2 conduction will result in large
currents owing through the power devices between the
high and low voltage motor rails.
To minimize dead time in a given design, the turn on of
LED2 should be delayed (relative to the turn o of LED1)
so that under worst-case conditions, transistor Q1 has just
turned o when transistor Q2 turns on, as shown in Figure
35. The amount of delay necessary to achieve this condition
is equal to the maximum value of the propagation delay
dierence specication, PDD
MAX
, which is specied to be
350 ns over the operating temperature range of -40°C to
125°C. Delaying the LED signal by the maximum propaga-
tion delay dierence ensures that the minimum dead time
is zero, but it does not tell a designer what the maximum
dead time will be. The maximum dead time is equivalent
to the dierence between the maximum and minimum
propagation delay dierence specications as shown in
Figure 36. The maximum dead time for the ACPL-312U is
700 ns (= 350 ns - (-350 ns)) over an operating tempera-
ture range of -40°C to 125°C.
Note that the propagation delays used to calculate PDD
and dead time are taken at equal temperatures and test
conditions since the optocouplers under consideration
are typically mounted in close proximity to each other and
are switching identical IGBTs.
V
O
– OUTPUT VOLTAGE – V
0
0
(V
CC
- V
EE
) – SUPPLY VOLTAGE – V
10
5
14
10 15
2
20
6
8
4
12
(12.3, 10.8)
(10.7, 9.2)
(10.7, 0.1)
(12.3, 0.1)
Figure 34. Under voltage lock out.
Figure 35. Minimum LED skew for zero dead time.
Figure 36. Waveforms for dead time.
