AD80066 Data Sheet
Rev. B | Page 18 of 20
ANALOG INPUTS—SHA MODE
Figure 19 shows the analog input configuration for the SHA
mode of operation. Figure 20 shows the internal timing for the
sampling switches. The input signal is sampled when CDSCLK2
transitions from high to low, opening S1. The voltage on the
OFFSET pin is also sampled on the falling edge of CDSCLK2,
when S2 opens. S3 is then closed, generating a differential
output voltage that represents the difference between the
sampled input voltage and the OFFSET voltage. The input
clamp is disabled during SHA mode operation.
AD80066
S1
2pF
S3
CML
INPUT SIGNAL
S2
2pF
CML
OFFSET
OPTIONAL DC OFFSET
(OR CONNECT TO GND)
VINA
VINB
VINC
VIND
A
B
C
D
CML
CML
CML
CML
CML
CML
08552-019
Figure 19. SHA Mode Input Configuration (All Four Channels Are Identical)
CDSCLK2
Q3
(INTERNAL)
S1, S2 CLOSED S1, S2 CLOSED
S3 CLOSED S3 CLOSED
S3 OPEN
S1, S2 OPEN
08552-020
Figure 20. SHA Mode Internal Switch Timing
Figure 21 shows how the OFFSET pin can be used in a CIS
application for coarse offset adjustment. Many CIS signals have
dc offsets ranging from several hundred millivolts to more than
1 V. By connecting the appropriate dc voltage to the OFFSET pin,
the large dc offset is removed from the CIS signal. Then, the
signal can be scaled using the PGA to maximize the dynamic
range of the ADC.
AD80066
OFFSET
A OFFSET
VINA
VINB
VINC
0.1µF
AVDD
VOLTAGE
REFERENCE
FROM CIS
MODULE
R1
B OFFSET
C OFFSET
DC OFFSET
R2
SHA
SHA
SHA
08552-021
Figure 21. SHA Mode Used with External DC Offset
PROGRAMMABLE GAIN AMPLIFIERS (PGA)
The AD80066 uses one PGA for each channel. Each PGA has a
gain range from 1× (0 dB) to 5.8× (15.5 dB), adjustable in
64 steps. Figure 22 shows the PGA gain as a function of the
PGA register value. Although the gain curve is approximately
linear-in-dB, the gain in V/V varies nonlinearly with register
code, following the equation
63
63
4.91
5.9
G
Gain
where G is the decimal value of the gain register contents and
varies from 0 to 63.
GAIN (V/V)
5.9
PGA REGISTER VALUE (Decimal)
0
GAIN (dB)
1
5
12
9
6
3
0
5.0
4.0
3.0
2.0
1.0
4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 63
08552-022
Figure 22. PGA Gain Transfer Function
Data Sheet AD80066
APPLICATIONS INFORMATION
CIRCUIT AND LAYOUT RECOMMENDATIONS
Figure 23 shows the recommended circuit configuration for
4-channel CDS mode operation. The recommended input
coupling capacitor value is 0.1 µF (see the Analog InputsCDS
Mode section). A single ground plane is recommended for the
AD80066. A separate power supply can be used for DRVDD,
the digital driver supply, but this supply pin should still be
decoupled to the same ground plane as the rest of the AD80066.
The loading of the digital outputs should be minimized, either
by using short traces to the digital ASIC or by using external
digital buffers. To minimize the effect of digital transients
during major output code transitions, the falling edge of
CDSCLK2 should occur coincident with or before the rising
edge of ADCCLK (see Figure 3 through Figure 8 for timing).
All 0.1 µF decoupling capacitors should be located as close as
possible to the AD80066 pins. When operating in 1-channel
mode, the unused analog inputs should be grounded.
Figure 24 shows the recommended circuit configuration for
4-channel SHA mode. All of the previously explained consid-
erations also apply to this configuration, except that the analog
input signals are directly connected to the AD80066 without the
use of coupling capacitors. Before connecting the signals, the
analog input signals must be dc-biased between 0 V and 1.5 V
or 3 V (see the Analog InputsSHA Mode section).
CLOCK
INPUTS
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD80066
AVDD
AVSS
A INPUT
DATA
INPUTS
3.3V
5V
5V
SERIAL
INTERFACE
VINA
OFFSET
VINB
CML
VINC
CAPT
CAPB
VIND
AVSS
AVDD
SLOAD
SCLK
SDATA
CDSCLK1
CDSCLK2
ADCCLK
DRVDD
DRVSS
(MSB) D7
D6
D5
D4
D3
D2
D1
(LSB) D0
C INPUT
D INPUT
B INPUT
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
1.0µF
0.1µF
0.1µF
10µF
0.1µF
0.1µF
08552-023
Figure 23. Recommended Circuit Configuration, 4-Channel CDS Mode
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
2
CLOCK
INPUTS
AVDD
DATA
INPUTS
3.3V
5V
CDSCLK1
CDSCLK2
ADCCLK
DRVDD
DRVSS
(MSB) D7
D6
D5
D4
D3
D2
D1
(LSB) D0
0.1µF
0.1
µF
TOP VIEW
(Not to Scale)
AD80066
A INPUT
5V
SERIAL
INTERFACE
C INPUT
D INPUT
B INPUT
0.1µF
0.1µF
0.1
µF
10µF
0.1µF
0.1
µF
AVSS
VINA
OFFSET
VINB
CML
VINC
CAPT
CAPB
VIND
AVSS
AVDD
SLOAD
SCLK
SDATA
08552-024
Figure 24. Recommended Circuit Configuration, 4-Channel SHA Mode (Analog Inputs Sampled with Respect to Ground)
Rev. B | Page 19 of 20
AD80066 Data Sheet
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-150-AH
060106-A
28
15
14
1
10.50
10.20
9.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 MIN
0.65 BSC
2.00 MAX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
Figure 25. 28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
AD80066KRSZ 0°C to 70°C 28-Lead SSOP RS-28
AD80066KRSZRL 0°C to 70°C 28-Lead SSOP RS-28
1
Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08552-0-4/15(B)
Rev. B | Page 20 of 20

AD80066KRSZRL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Complete 16B CCD/ CIS Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet