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AD80066KRSZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Data Sheet AD80066
SPECIFICATIONS
ANALOG SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS mode, f
ADCCLK
= 24 MHz, f
CDSCLK1
= f
CDSCLK2
= 6 MHz, PGA gain = 1, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit
MAXIMUM CONVERSION RATE
4-Channel Mode with CDS 24 MSPS
3-Channel Mode with CDS 24 MSPS
2-Channel Mode with CDS 24 MSPS
1-Channel Mode with CDS 12 MSPS
ACCURACY (ENTIRE SIGNAL PATH)
ADC Resolution 16 Bits
Integral Nonlinearity (INL) +20/−5 LSB
Differential Nonlinearity (DNL) ±0.5 LSB
No Missing Codes Guaranteed
ANALOG INPUTS
Input Signal Range
1
1.5/3.0 V p-p
Allowable Reset Transient
1
2.0 V
Input Limits
2
AVSS − 0.3
V
Input Capacitance
10
pF
Input Bias Current 10 nA
AMPLIFIERS
PGA Gain Range 1 5.9 V/V
PGA Gain Resolution
2
64 Steps
PGA Gain Monotonicity Guaranteed
Programmable Offset Range −305 +295 mV
Programmable Offset Resolution 512 Steps
Programmable Offset Monotonicity
Guaranteed
NOISE AND CROSSTALK
Total Output Noise at PGA Minimum
9.5
LSB rms
Total Output Noise at PGA Maximum
35
LSB rms
Channel-to-Channel Crosstalk
@ 24 MSPS 70 dB
@ 12 MSPS 90 dB
POWER SUPPLY REJECTION
AVDD = 5 V ± 0.25 V 0.1 % FSR
VOLTAGE REFERENCE (T
A
= 25°C)
CAPT − CAPB 0.75 V
TEMPERATURE RANGE
Operating 0 70 °C
Storage −65 +150 °C
POWER SUPPLIES
AVDD 4.5 5.0 5.25 V
DRVDD 3.0 3.3 5.25 V
OPERATING CURRENT
AVDD 95 mA
DRVDD 4 mA
Power-Down Mode Current 300 µA
Rev. B | Page 3 of 20
AD80066 Data Sheet
Parameter Min Typ Max Unit
POWER DISSIPATION
4-Channel Mode at 24 MHz 490 mW
1-Channel Mode at 12 MHz 300 mW
4-Channel Mode at 8 MHz, Slow Power Mode
3
165 mW
1
The linear input signal range is up to 3 V p-p when the CCD reference level is clamped to 3 V by the AD80066 input clamp (see Figure 2).
2
The PGA gain is approximately linear-in-dB but varies nonlinearly with register code (see the Programmable Gain Amplifiers (PGA) section for more information).
3
Measured with Bit D1 of the configuration register set high for 8 MHz, low power operation.
2V TYP
RESET TRANSIENT
AVDD = 5V
3V BIAS SET BY INPUT CLAMP
1.5V OR 3V p-p MAX INPUT SIGNAL RANGE
GND
08552-002
Figure 2. Input Signal with the CCD Reference Level Clamped to 3 V
DIGITAL SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V, CDS mode, f
ADCCLK
= 24 MHz, f
CDSCLK1
= f
CDSCLK2
= 6 MHz, C
L
= 10 pF, unless otherwise noted.
Table 2.
Parameter Symbol Min Typ Max Unit
LOGIC INPUTS
High Level Input Voltage V
IH
2.0 V
Low Level Input Voltage V
IL
0.8 V
High Level Input Current I
IH
10 µA
Low Level Input Current
I
IL
10
µA
Input Capacitance
C
IN
10
pF
LOGIC OUTPUTS (DRVDD = 5 V)
High Level Output Voltage (I
OH
= 2 mA) V
OH
4.5 V
Low Level Output Voltage (I
OL
= 2 mA) V
OL
0.5 V
LOGIC OUTPUTS (DRVDD = 3 V)
High Level Output Voltage (I
OH
= 2 mA) V
OH
2.5 V
Low Level Output Voltage (I
OL
= 2 mA)
V
OL
0.5
V
Rev. B | Page 4 of 20
Data Sheet AD80066
TIMING SPECIFICATIONS
T
MIN
to T
MAX
, AVDD = 5 V, DRVDD = 5 V.
Table 3.
Parameter Symbol Min Typ Max Unit
CLOCK PARAMETERS
4-Channel Pixel Rate t
PRA
166 ns
1-Channel Pixel Rate t
PRB
83 ns
ADCCLK Pulse Width t
ADCCLK
20 ns
CDSCLK1 Pulse Width t
C1
15 ns
CDSCLK2 Pulse Width t
C2
15 ns
CDSCLK1 Falling
1
to CDSCLK2 Rising t
C1C2
0 ns
ADCCLK Falling to CDSCLK2 Rising t
ADC2
0 ns
CDSCLK2 Rising to ADCCLK Rising t
C2ADR
5 ns
CDSCLK2 Falling
1
to ADCCLK Falling t
C2ADF
20 ns
CDSCLK2 Falling
1
to CDSCLK1 Rising t
C2C1
5 ns
Aperture Delay for CDS Clocks t
AD
2 ns
SERIAL INTERFACE
Maximum SCLK Frequency, Write Operation f
SCLK
50 MHz
Maximum SCLK Frequency, Read Operation f
SCLK
25 MHz
SLOAD to SCLK Setup Time t
LS
5 ns
SCLK to SLOAD Hold Time t
LH
5 ns
SDATA to SCLK Rising Setup Time t
DS
2 ns
SCLK Rising to SDATA Hold Time t
DH
2 ns
SCLK Falling to SDATA Valid t
RDV
10 ns
DATA OUTPUT
Output Delay t
OD
8 ns
Latency (Pipeline Delay)
3 (fixed)
Cycles
1
CDSCLKx falling edges should not occur within the first 10 ns following an ADCCLK edge.
Timing Diagrams
ANALOG
INPUTS
CDSCLK1
CDSCLK2
ADCCLK
OUTPUT
DATA
(D[7:0])
PIXEL n (A,B,C,D)
PIXEL (n + 1)
t
AD
t
AD
t
C2ADF
t
C2ADR
t
ADC2
t
OD
t
ADCCLK
t
ADCCLK
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
HIGH
BYTE
LOW
BYTE
C(n – 2)B(n – 2) C(n – 2) D(n – 2) D(n – 2)
A(n – 1) A(n – 1) B(n – 1) B(n – 1) C(n – 1) C(n
– 1) D(n – 1) D(n – 1) A(n) A(n) B(n)
t
PRA
t
C2C1
t
C1C2
t
C2
t
C1
08552-003
Figure 3. 4-Channel CDS Mode Timing
Rev. B | Page 5 of 20
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD80066KRSZRL

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Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Complete 16B CCD/ CIS Signal Processor
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