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AD80066KRSZRL
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
AD80066
Data Sheet
t
OD
t
ADCCLK
t
ADCCLK
ANALO
G
INPUT
S
CDSCLK1
CDSCLK2
ADCCLK
OUT
PUT
DATA
(D[7:0
])
PIXE
L n (A, B
, C)
PIXEL (n + 1)
PIXEL (n + 2)
t
AD
t
AD
t
PRA
t
C2C1
t
C1
t
C2
t
C1C2
t
C2ADF
t
C2ADR
t
ADC2
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
B(n
– 2)
A(n
– 2)
B(n
– 2)
C(n
– 2)
C(
n
– 2)
A(
n
– 1)
A(n
– 1)
B(n
– 1)
B(
n
– 1)
C(
n
– 1)
C(
n
– 1)
A(n
)
A(n)
B(n
)
B(n)
08552-004
Figure
4
. 3
-
Chan
nel CDS Mode T
iming
CH 1 (n
– 2)
CH 2 (n
– 2)
CH 1 (n
– 1)
CH 2 (
n – 1)
CH 1 (n
)
ANALO
G
INPUT
S
CDSCLK1
CDSCLK2
ADCCLK
OUT
PUT
DATA
(D[7:0
])
PIXEL n
PIXEL (n + 1)
PIXEL (n + 2)
t
AD
t
AD
t
PRA
t
C2C1
t
C1
t
ADCCLK
t
ADCCLK
t
C2
t
C1C2
t
C2ADR
t
C2ADF
t
ADC2
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
08552-005
Figure
5
. 2
-
Chan
nel CDS Mode T
iming
Rev.
B
| P
a
ge
6
of
20
Data Sheet
AD80066
ANALO
G
INPUT
S
CDSCLK1
PIXEL n
PIXEL (n + 1)
PIXEL (n + 2)
CDSCLK2
ADCCLK
OUT
PUT
DATA
(D[7:0
])
NOTE
S
1. I
N 1-CHANNEL
CDS M
ODE
. T
HE CDS
CLK1 F
ALL
I
NG E
DGE
AND THE
CDSCL
K2 RIS
ING
EDG
E MUS
T O
CCUR W
HIL
E ADCCL
K IS
LO
W
.
LOW
BYTE
HIGH
BYTE
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
08552-006
t
AD
t
C1
t
AD
t
C2ADR
t
OD
t
C1C2
PIXEL (n – 4)
t
C2ADF
t
ADCCLK
t
ADCCLK
t
C2
PIXEL (n – 4)
PIXEL (n – 3)
PIXEL (n
– 3)
PIXEL (n – 2)
PIXEL (n – 2)
t
C2C1
t
PRB
Figure
6
. 1
-
Chan
nel CDS Mode T
iming
PIXEL
n (A,
B, C,
D)
t
AD
t
C2
t
C2ADF
t
ADC2
t
C2ADR
t
ADCCLK
t
ADCCLK
t
OD
C(n
– 2)
D(n
– 2)
D(n
– 2)
A(n
– 1)
A(n
– 1)
A(n
)
A(n
)
B(n
)
B(n
)
HIGH
BYT
E
LOW
BYT
E
HIGH
BYT
E
LOW
BYT
E
HIGH
BYT
E
LOW
BYT
E
HIGH
BYT
E
LOW
BYT
E
HIGH
BYT
E
LOW
BYT
E
HIGH
BYT
E
LOW
BYT
E
HIGH
BYT
E
LOW
BYT
E
t
P
RA
PIXEL
(n +
1
)
ANALO
G
INPUT
S
CDSCL
K2
ADCCLK
OUT
PUT
D
AT
A
(D[7:0
])
B(n
– 1)
B(n
– 1)
C(n
– 1)
C(n – 1)
D(n – 1)
D(n – 1)
08552-007
Figure
7
. 4
-
Chan
nel SHA Mo
de Timing
Rev.
B
| P
a
ge
7
of
20
AD80066
Data Sheet
Rev. B | Page 8
of 20
ANALO
G
INPU
TS
CDSCLK2
ADCCLK
OUT
PUT
DATA
(D[7:0])
t
OD
PIXEL n
t
AD
HIGH BY
T
E
LO
W BYT
E
LO
W BYT
E
HIGH BY
T
E
HIGH
BYT
E
LO
W BYT
E
PIXEL (n – 4)
PIXEL (n – 4)
PIXEL
(n – 3)
PI
XEL (n – 3)
PIXEL (n – 2)
PI
XEL (n – 2)
t
C2ADR
t
C2
t
PRB
t
C2ADF
t
ADCCLK
t
ADCCLK
0
8552-008
PIXEL (n + 1)
Figure 8. 1-Chann
el SHA Mode Ti
ming
t
OD
t
OD
HIG
H BYTE
(DB[
15:8])
HIG
H BYTE
(DB[15:
8])
LOW BY
TE
(DB[7:
0])
LOW BYTE
(DB[
7:0])
HIG
H BYTE
(DB[15:8]
)
ADCCLK
OUT
PUT
DATA
(D[7:0])
LOW BY
TE
(DB[7:
0])
PIXEL n
PIXEL n
0
8552-009
PIXEL (
n + 1)
PIXEL (
n + 1
)
PIXEL (
n + 2
)
PIXEL (
n + 3)
Figure 9. Digital Output Data Timing
t
OD
ADCCLK
OUTPU
T DA
T
A
(D[7:0])
PIXEL n
PIXEL (n + 1)
HIGH
BYTE
(DB[15:
8])
HI
GH
BYTE
(DB[15:
8])
HIGH
BYTE
(DB[15:8
])
08552-010
PIXEL (n + 2)
Figure 10. Single-Byte Mode Digital Output Data Timing
t
LH
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
DS
t
LS
t
DH
A0
A2
R/
W
SDATA
A1
SCLK
SLO
AD
A3
0
8552-01
1
Figure 11. Serial Wr
ite Operation Ti
ming
t
LH
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
RDV
t
LS
A1
A3
A2
SDATA
SCLK
S
LOAD
A0
R/W
08552-012
Figure 12. Serial Re
ad Operation
Timing
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
AD80066KRSZRL
Mfr. #:
Buy AD80066KRSZRL
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC Complete 16B CCD/ CIS Signal Processor
Lifecycle:
New from this manufacturer.
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