ISL99227, ISL99227B
11
FN8684.2
October 27, 2016
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Operation
The ISL99227, ISL99227B are optimized drivers and power
stage solutions for high density synchronous DC/DC power
conversion. They include high performance GH and GL drivers, an
NFET controlled to function as a bootstrap diode and MOSFET
pair optimized for high switching frequency buck voltage
regulators. They also include advanced power management
features listed as follows:
1. Accurate current and thermal reporting outputs.
2. Fault protections of HFET overcurrent, HFET short,
over-temperature, VCC UVLO and VIN UVLO.
Power-On Reset (POR)
During initial start-up, the V
CC
voltage rise is monitored. Once the
rising V
CC
voltage exceeds 3.86V (typical) for 125µs, then normal
operation of the driver is enabled. The PWM signals are passed
through to the gate drivers, the TMON output is valid and the
IMON-REFIN output starts at zero, and becomes valid on the first
GL signal. If V
CC
drops below the falling threshold of 3.58V
(typical), operation of the driver is disabled. The PVCC voltage is
not monitored as it should to be from the same supply as V
CC
.
V
IN
POR is also monitored. When both V
CC
and V
IN
reach above
their POR trip points, it enables HFET overcurrent protection.
Both V
CC
and V
IN
POR are gated to the FAULT# pin, which goes
high once both V
CC
and V
IN
are above their POR levels after
125µs and no other faults occur.
Shoot-Through Protection
Prior to POR, the undervoltage protection function is activated
and both GH and GL are held active low (HFET and LFET off). After
POR (the Rising Thresholds; see “Electrical Specifications” on
page 8
) and a 125µs delay, the PWM and LGCTRL signals are
used to control both high-side and low-side MOSFETs, as shown
in Table 2.
The ISL99227, ISL99227B’s dead time control is optimized for
high efficiency and guarantees that simultaneous conduction of
both FETs cannot occur.
Should the driver have no bias voltage applied (either V
CC
or
PVCC missing) and be unable to actively hold the MOSFETs off,
an integrated 20kΩ resistor from the upper MOSFET
gate-to-source will aid in keeping the HFET device in its off state.
This can be especially critical in applications where the input
voltage rises prior to the ISL99227, ISL99227B V
CC
and PVCC
supplies.
Tri-State PWM Input
The ISL99227 supports a 3.3V PWM tri-level input and is
compatible with Intersil’s digital multiphase controllers as well
as other control IC’s utilizing 3.3V PWM logic. Use the ISL99227B
for 5V PWM logic, like ISL6617A doubler with 5V PWM logic
output (see Table 1 on page 5
). Should the pin be pulled into and
remain in the tri-state window for a set hold-off time, the driver
will force both MOSFETs to their off states. When the PWM signal
moves outside the shutdown window, the driver immediately
resumes driving the MOSFETs according to the PWM commands.
This feature is utilized by Intersil’s PWM controllers as a method
of forcing both MOSFETs off. Should the PWM input be left
floating, the pin will be pulled into the tri-state window internally
and thus force both MOSFETs to a safe off state.
Although the PWM input can sustain a voltage as high as V
CC
,
the ISL99227 is not compatible with a controller (such as the
ISL63xx family) that actively drives its mid-level in tri-state higher
than 1.7V.
Bootstrap Function
The ISL99227, ISL99227B feature an internal NFET that is
controlled to function as a bootstrap diode. A high quality
ceramic capacitor should be placed in close proximity across the
BOOT and PHASE pins. The bootstrap capacitor can range
between 0.1µF~0.22µF (0402~0603 and X5R~X7R) for normal
buck switching applications.
Current Monitoring
LFET current is monitored and a signal proportional to that
current is the output on the IMON pin (relative to the REFIN pin).
The IMON and REFIN pins should be connected to the appropriate
current sense input pin of the controller. This method does not
require external R
SENSE
or DCR sensing of the inductor current.
Figure 12
depicts the low-side current sense concept. After the
falling edge of the PWM, there are two delays; one that
represents the expected propagation delay from PWM to GH/SW
and a second blanking delay to allow time for the transition to
settle; typical total time is ~350ns. The IMON output
approximates the actual I
L
waveform.
TABLE 2. GH AND GL OPERATION TRUTH TABLE
PWM LGCTRL GH GL HFET, LFET COMMENT
3-state X 0 0 Both off
0101LFET onNormal
1110HFET onNormal
0000LFET offGL low
1010HFET onNormal
FIGURE 12. LFET CURRENT SAMPLE DIAGRAM
ONdly
OFFdly
SW
GL
GH
PWM
IL x IMON
GAIN
IMON
