ISL99227, ISL99227B
13
FN8684.2
October 27, 2016
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FAULT Reporting
Overcurrent and shorted HFET detections will pull the IMON pin to
a high (fault) level, such that the PWM controller should quickly
recognize it as out of the normal range. Over-temperature
detection will pull the TMON pin to a high (fault) level, such that
the PWM controller should quickly recognize it as out of the
normal range.
All of the above faults, plus the VCC and VIN POR (UVLO)
conditions, will also pull down the FAULT# pin. This can be used
by the controller (or system) as a fault detection and can also be
used to disable the controller through its Enable pin.
The fault reporting and respective SPS response are summarized
in Table 3
.
PCB Layout Considerations
Proper PCB layout will reduce noise coupling to other circuits,
improve thermal performance and maximize the efficiency. The
following is meant to lead to an optimized layout:
• Place multiple 10µF or greater ceramic capacitors directly on
the device between VIN and GND as indicated in Figure 15 on
page 14. This is the most critical decoupling and reduced
parasitic inductance in the power switching loop. This will
reduce overall electrical stress on the device as well as reduce
coupling to other circuits. Best practice is to place the
decoupling capacitors on the same PCB side as the device. For
a design with tight space requirements, these decoupling
capacitors can be placed under the device, i.e., bottom layer,
as shown in Figure 17 on page 15
.
• Connect GND to the system GND plane with a large via array as
close to the GND pins as design rules allow. This improves
thermal and electrical performance.
• Place PVCC, VCC and BOOT-PHASE decoupling capacitors at
the IC pins as shown in Figure 15 on page 14.
• Note that the SW plane connecting the ISL99227, ISL99227B
and inductor must carry full load current and will create
resistive loss if not sized properly. However, it is also a very
noisy node that should not be oversized or routed close to any
sensitive signals. Best practice is to place the inductor as close
to the device as possible and thus minimizing the required
area for the SW connection. If one must choose a long route of
either the VOUT side of the inductor or the SW side, choose the
quiet VOUT side. Best practice is to locate the ISL99227,
ISL99227B as close to the final load as possible and thus
avoid noisy or lossy routes to the load.
• The IMON and IREF network and their vias should not sit on the
top of the VIN plane, a keep out area is recommended, as
shown in Figure 17 on page 15
.
• The PCB is the best thermal heatsink material than any top
side cooling materials. The PCB always has enough vias to
connect VIN and GND planes. Insufficient vias will yield lower
efficiency and very poor thermal performance.
Figures 16
and 17 show a multiphase PCB layout example for
dual footprint, a device compatible with ISL99227. For a
reference design file, please contact Intersil’s Application
support at www.intersil.com/en/support.html
.
TABLE 3. FAULT REPORTING SUMMARY
FAULT
EVENT IMON TMON FAULT# RESPONSE
OC HIGH N/A LOW GH gated off. The controller
should acknowledge and force its
PWM to tri-state to keep both
HFET and LFET off. The fault is
cleared ~1µs after PWM enters
tri-state, otherwise, it stays
asserted. (If system OVP occurs,
the controller may send PWM low
to turn on LFET).
Shorted
HFET
IMON
Latched
HIGH
N/A FAULT#
Latched
LOW
GH gated off, until fault latch is
cleared by VCC POR. GL follows
PWM.
OT N/A HIGH LOW GH and GL follow PWM.
VCC
UVLO
IMON-
REFIN =
0V
TMON
Not
Valid
LOW Switching stops while in UVLO.
Once above VCC POR, after
125µs: GH and GL follow PWM;
the FAULT# pin is released; TMON
is valid; IMON-REFIN is valid after
GL first goes low.
VIN
UVLO
OC not
valid
N/A LOW GH and GL follow PWM.
