ISL99227, ISL99227B
6
FN8684.2
October 27, 2016
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Pin Configuration
ISL99227, ISL99227B
(32 LD PQFN)
TOP VIEW
1
4
2
3
5
8
6
7
91110 12 13 14 15 16
17
18
19
20
21
22
23
32 3031 29 28 27 26 25
24
LGCTRL
VCC
PV CC
GND
NC
GND
GND
GND
GND
GND
GND
GND
VI N
VI N
VI N
SW
SW
SW
SW
SW
SW
SW
SW
IMON
REFIN
GND
PWM
VI N
FAULT#
BOOT
PHASE
TMON
VIN
34
GND
35
GND
33
Pin Descriptions
PIN # PIN NAME DESCRIPTION
1 LGCTRL Lower gate control signal input. LO = GL low (LFET off). HI = Normal operation (GL and GH strictly obey PWM). This pin should
be driven with a logic signal, or externally tied high if not required; it should NOT be left floating.
2 VCC +5V logic bias supply. Place a high quality low ESR ceramic capacitor (~1µF/X7R) in close proximity from this pin to GND.
3 PVCC +5V gate drive bias supply. Place a high quality low ESR ceramic capacitor (~1µF/X7R) in close proximity from this pin to
GND.
4, 6, 7, 8, 17,
18, 19, 20, 29
33, 35
GND All GND pins are internally connected. Pins 4 and 29 should be connected directly to the nearby GND paddles on package
bottom. Figure 15 on page 14
shows GND paddles should be connected to the system GND plane with as many vias as
possible to maximize thermal and electrical performance.
5 NC No connect (this is a low-side gate driver output (GL), optional to monitor for system debugging).
9, 10, 11, 12,
13, 14, 15, 16
SW Switching junction node between HFET source and LFET drain. Connect directly to output inductor.
21, 22, 23, 27,
34
VIN Input of power stage (to drain of HFET). Place at least 2 ceramic capacitors (10µF or higher, X5R or X7R) in close proximity
across VIN and GND. Pin 27 should NOT be used for decoupling. For optimal performance, place as many vias as possible
in the bottom side VIN paddle.
24 PHASE Return of boot capacitor. Internally connected to SW node so no external routing required for SW connection.
25 BOOT Floating bootstrap supply pin for the upper gate drive. Place a high quality low ESR ceramic capacitor (0.1µF~0.22µF/X7R)
in close proximity across BOOT and PHASE pins.
26 FAULT# Open-drain output pin. Any fault (overcurrent, over-temperature, shorted HFET, or POR/UVLO) will pull this pin to ground. This
pin may be connected to the controller Enable pin or used to signal a fault at the system level.
28 PWM ISL99227: PWM input of gate driver, compatible with 3.3V tri-state PWM signal. ISL99227B for 5V PWM.
30 REFIN Input for external reference voltage for IMON signal. This voltage should be between 0.8V and 1.6V. Connect REFIN to the
appropriate current sense input of the controller. Place a high quality low ESR ceramic capacitor (~ 0.1µF) in close proximity
from this pin to GND.
31 IMON Current monitor output, referenced to REFIN. IMON will be pulled high (to REFIN + 1.2V) to indicate an HFET shorted or
overcurrent fault. Connect the IMON output to the appropriate current sense input of the controller. No more than 56pF
capacitance can be directly connected across IMON and REFIN pins. With a 100Ω series resistor, up to 470pF may be used.
32 TMON Temperature monitor output. For multiphase, the TMON pins can be connected together as a common bus; the highest voltage
(representing the highest temperature) will be sent to the PWM controller. TMON will be pulled high (to 2.5V) to indicate an
over-temperature fault. No more than 470pF total capacitance can be directly connected across the TMON and GND pins;
with a series resistor, a higher capacitance load is allowed, such as 1kΩ for 100nF load.
