System features introduction STA2064
12/19 Doc ID 16057 Rev 3
3 System features introduction
In this chapter, an introduction to the main STA2064 system features is given. These will be
explained in detail later in this document.
3.1 Power region partition
STA2064 is a device targeted to wide range of applications, starting from handheld battery
powered devices thanks to an optimzed power management but also addressing in dash
automotive power requirements thanks to its flexibile multivoltage IO.
Three main power regions are identified:
● V
dd_on
: It is the core voltage that powers the RTC (real-time clock), the PMU (Power
Management Unit), SRC (System Clock and Reset controller) and the Backup RAM of
STA2064. V
dd_on
remains usually powered even when the device is in DEEP-SLEEP
mode. For this reason, the static power consumption of this region stays below 20uA
worst case.
● V
dd
: It is the core voltage that powers the overall chip (apart from the IOs). This voltage
is not applied in very low power state condition. When applied, the V
dd_on
and V
dd
are
at the same voltage. A maximum of 10% variation between the two regions is required.
● V
ddio
: It is the power region dedicated to the IOs. The overall IOs are divided in seven
groups and each of them can be powered at different, independent voltages. Some
groups may have specific constraint in terms of power voltage range in order to meet
specific electrical characteristic compliant to some standards; some of these groups
are, for example, in the DDR interface and the 1.1 embedded USB transceiver. There is
also a group of IOs called V
ddio_on
that identifies the IOs that must be always powered
(also in the lowest power consumption state of STA2064) in order to make the wake-up
possible. The other five regions (called also V
ddiox
) can not be powered while in this
state. For more information, please refer to Chapter 3.6: IO groups on page 16.
3.2 Frequency region partition
STA2064 is designed so that there are two PLLs. PLL1 generates clock frequencies for the
ARM core and the internal buses, while the PLL2 generates clock frequencies for each
peripheral kernel and also for each peripheral interface. This means that each peripheral
receives the clock derived from the PLL1 at its internal interface, then it works with the clock
derived from the PLL2. Despite the use of two PLLs, a single system clock input or a single
external crystal is needed (in addition to the RTC clock (or crystal)).
