STA2064N Datasheet STA2064N2, STA2064N | P13-P15

STA2064 System features introduction

Doc ID 16057 Rev 3 13/19

3.3 Frequency and power range

The core voltage range is 1.25 ±4 %V while the IO voltage ranges are 1.8 ±10 %V,

2.5 ± 10 %V and 3.3 ± 10 %V.

Tabl e 2 shows some use cases of STA2064 in NORMAL mode:

The background of Tabl e 2 is the maximization of data throughput on the DRAM interface,

matching the currently available DRAM speed grades: 133 MHz, 166 MHz and 200 MHz (LP

DDR) and 333 MHz (DDR2). Despite this, it is possible to program the ARM core, the

internal bus and the DDR to run at different speeds than the ones mentioned in Ta bl e 2 The

ARM bus clock and the bus clock are derived from the same common source (VCO of the

PLL1) but are asynchronous each other. The DDR frequency can be the same

(synchronous) or derived with a different prescaling (1,2,3,4,5,6,8,9 or 10) from the VCO of

PLL1 or PLL2 (asynchronous configuration).

STA2064 embeds a complete GPS subsystem where both gate logic and dedicated DSP

work together. There are specific constraints in this subsystem in terms of minimum

frequency in order to guarantee the target GPS specifications.

In the lowest power consumption state as possible, only V

dd_on

is powered and the target

current drawn is 20 μA. In this state, the clock is not running and the current leakage is

mainly due to the Backup memory. The 20 μA current limit has to be considered with

Process best (leakage worst case condition), V

dd_on

1.3V (1.25V plus 4% tolerance) and

Junction Temperature 50

C (considering, while in this state, the ambient temperature is

equal to the junction temperature).

Table 2. Frequency and power use cases

and V

dd_on

(V)

Core Freq

[MHz]

Bus Freq

[MHz]

DDR Freq

[MHz]

Sync/Async

[S/A]

1.2 5(±4%) 533 177.67 177.67 S

1.2 5(±4%) 533 133.25 133.25 S

1.2 5(±4%) 533 177.67 312 A, DDR2

1.2 5(±4%) 520 208 130 A

1.2 5(±4%) 520 173.34 173.34 S

1.2 5(±4%) 520 130 130 S

1.2 5(±4%) 520 208 312 A, DDR2

1.2 5(±4%) 494 197.6 197.6 S

1.2 5(±4%) 494 164.67 164.67 S

1.2 5(±4%) 494 123.5 123.5 S

1.2 5(±4%) 494 208 329.34 A, DDR2

System features introduction STA2064

14/19 Doc ID 16057 Rev 3

3.4 Power states

The following power states are defined:

● OFF: V

dd_on

and V

are not applied (all data in the backup RAM is lost): no data

retention is kept in the SDRAM

● NORMAL: Each peripheral runs at its nominal speed with the possibility of turning off

all the unused peripherals (peripheral kernel clock gated)

● SLOW: PLL1 bypassed. ARM and bus runs at crystal clock. PLL2 runs at its nominal

speed. PLL1 can be optionally put in power down

● DOZE: It is like SLOW mode with the ARM running either at 19 MHz or 32 kHz

● STANDBY: PLLs run at their nominal speed. Clocks are gated, ARM in WFI (Wait For

Interrupt) state

● DEEP-SLEEP: V

powered off. V

dd_on

powered (RTC, few GPIOs, backup RAM) and

clocked at 32 kHz making the wakeup possible. The context is put in the external

SDRAM while in self refresh mode. Only the V

ddio_on

region must be powered

● SLEEP: It is like the DEEP-SLEEP mode, with the difference that V

and V

ddio

are

also applied and all the PLLs are off (optional for PLL2)

● BACKUP: It is like DEEP-SLEEP, with the difference that the context is not saved in the

external SDRAM. When coming out from Backup to any power state, the ARM core will

execute the first code instruction after 2ms from power on reset release.

While in NORMAL, SLOW AND STANDBY, V

dd_on

and V

are the same (10% tolerance

between them) and cannot be changed. Also the power to the several IO groups is kept

unchanged.

In order to change the V

dd_on

and V

values, the system has to transit to either OFF,

SLEEP, DEEP-SLEEP or BACKUP and then back to the selected state.

In order to keep the power consumption as low as possible, the target voltage mentioned in

DEEP-SLEEP is considered at 1.0V.

A dedicated FSM manages the power state transitions among NORMAL, SLOW, DOZE

AND SLEEP. All other states mentioned above are SW variants of the ones managed by the

FSM.

Tabl e 3 shows the summary of the power states supported by STA2064.

Table 3. Power mode states

Power State 32 kHz PLL1 PLL2 V

dd_on

IOs

OFF off off off off off off

NORMAL on on on 1.2V to 1.3V =V

dd_on

1.7 to 3.6V

SLOW on

Off. Bypassed by

main oscillator

off (SW can

take it on)

1.2V to 1.3V =

Vdd_on

1.7 to 3.6V

DOZE on

Off. Bypassed by

32 kHz

off (SW can

take it on)

1.2V to 1.3V =V

dd_on

1.7 to 3.6V

STANDBY on

on (clk gated)

ARM in WFI

on (clk gated) 1.2V to 1.3V =V

dd_on

1.7 to 3.6V

SLEEP on off

off (SW can

take it on)

1.2V to 1.3V

(typically 1.25V)

dd_on

1.7 to 3.6V

STA2064 System features introduction

Doc ID 16057 Rev 3 15/19

3.5 System wakeup and power down

Typically the system using STA2064 will never be powered off, even when the user switches

the device off using the main power switch. The main power switch works in a way that puts

the device either in Backup or in DEEP-SLEEP mode. In this state, the only blocks within

STA2064 that are powered are the RTC, PMU, PWL, SRC and the backup RAM; at system

level, only the V

dd_on

is powered.

The following wakeup methods are possible:

● The user presses a button on the unit that causes all of the main power supplies to

start. After an appropriate delay, the processor's reset line is lifted and allows the code

to start executing

● The internal alarm feature triggers a dedicated signal that will cause all of the main

supplies to start. After an appropriate delay, the processor's reset line is lifted and

allows the code to start execution

Considering the above mentioned wakeup system, while in DEEP-SLEEP and in BACKUP

state also, some dedicated IO lines must be powered:

● POR (input)

● POWEREN (output)

● VDDOK and BATOK (input)

● WAKE (input)

● 32 kHz crystal (SXTALI and SXTALO)

● OSC32KOUT (output)

In order to keep the external DRAM in self refresh while in DEEP-SLEEP, CKE of the DRAM

must be kept low. Since all the IOs are not powered in DEEP-SLEEP, in order to make the

self refresh working, an external pulldown resistor is needed.

DEEP-SLEEP on off off

1.2V to 1.3V

(typically 1.25V)

off

Refer section

3.5

BACKUP on off off

1.2V to 1.3V

(typically 1.25V)

off

Refer section

3.5

Table 3. Power mode states (continued)

Power State 32 kHz PLL1 PLL2 V

dd_on

IOs

OFF off off off off off off

NORMAL on on on 1.2V to 1.3V =V

dd_on

1.7 to 3.6V

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P19

STA2064N

Mfr. #:

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Manufacturer:

STMicroelectronics

Description:

RF Microcontrollers - MCU Infotainment ARM1176 533MHz 8 GPS 512Byte

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