STA2064 System description
Doc ID 16057 Rev 3 7/19
2.4.2 DDR-SDRAM controller
The SDRAM controller has been designed to support up to 1Gbit over each of the two chip
selects (or up to 2 Gbit over a single chip select) of:
LP DDR-SDRAM
DDR2
The memory data bus will be 16 or 32-bit wide for LP DDR-SDRAM memories (under
software control). This same configuration is also supported for DDR2 type of memories,
with two 16-bit devices per chip select.
2.5 Audio/video functions
2.5.1 C3
It is composed of CD-ROM Decoder Block, responsible for performing sector descrambling
and 3
rd
level of error correction embedded in the sector specific to CD-ROM mode1 and XA
Form1, and Data Filter block supporting frame data filtering and different block layout
organization possibilities. The C3 block can take its input data directly from SPDIF or from
the memory space, and delivers back its output data to memory, supporting DMA requests.
2.5.2 Sample rate converter (SaRaC)
This block offers a fully digital stereo asynchronous sample rate conversion, using an
automatic Digital Ratio Locked Loop. Its main features are:
Up to 20-bit input and 22-bit output sample size
DMA optimized 16-bit stereo sample interface
Input sample rate from selectable MSP or SPDIF interface (32 kHz to 48 kHz)
Output sample rate from selectable MSP interface (44.1 kHz to 48 kHz)
Internally generated input sample rate (8 kHz to 48 kHz) for compressed audio
decoding
2.5.3 JPEG decoder
The JPEG decoder block performs Baseline DCT sequential decoding up to 16Mpix/sec.
JPEG compressed thumbnails are also supported.
2.5.4 Smart graphic accelerator (SGA)
The smart graphic accelerator (SGA) provides an efficient 2D and 3D primitive drawing tool
that breaks down the MIPS and power consumption concerns of pixel processing.
2.5.5 Color LCD controller (CLCD)
This interface drives LCD panels. It supports single or dual-panel color and monochrome
STN displays and color TFT or HR-TFT displays. The resolution can be 1, 2 or 4 bits-
perpixel (bpp) palletized for mono STN, 1, 2, 4 or 8 bpp palletized for color STN and TFT,
16-bpp true-color non palletized for Color STN and TFT, 18-bpp packed or not packed
truecolor non pallettized for color TFT. It also offers Frame Modulation to deliver enhanced
colors on 12, 16 or 18 bits (HR-) TFT panels from up to 18-bpp format.
System description STA2064
8/19 Doc ID 16057 Rev 3
2.6 Communication interfaces
2.6.1 USB
STA2064 embeds one USB2.0 OTG high-speed interface, featuring:
a) High-speed signalling rate at 480 Mbit/s
b) Support for full-speed (12 Mbit/s) signaling bit rate
c) Support for session request protocol (SRP) and host negotiation protocol (HNP)
d) Up to 7 bidirectional endpoints plus control endpoint 0
e) 8192 bytes maximum FIFO dimension
f) Dynamic FIFO allocation
To reduce total system cost, it is equipped with a built-in USB 2.0 PHY.
With the goal of reducing the BOM cost for the customer, the USB 2.0 PHY also supports
this additional muxing scheme:
the USB D- wire is used as either the USB D- signal or UART receive data signal
the USB D+ wire is used as either the USB D+ signal or the UART transmit data signal
2.6.2 UART
STA2064 features four Autobaud UARTs. One offers all modem control/status signals. They
are enhanced version of the industry-standard 16C550 UART.
2.6.3 I
2
C
The I
2
C controller is an interface designed to support the physical and data link layer
according to I
2
C standard revision 2.1 (January 2000). The I
2
C bus is a 2-wire serial bus
that provides a low-cost interconnection between ICs. STA2064 features three I
2
C
interfaces.
2.6.4 MSP
The multichannel serial port (MSP) is a synchronous receive and transmit serial interface.
STA2064 features three MSPs.
2.6.5 SSP
STA2064 features two SSPs up to 24Mbit/sec for synchronous serial communication with
external peripherals. SPI, MicroWire, T.I. and mono-directional protocols are supported with
programmable word length up to 32 bits.
2.6.6 SPDIF
This interface takes SPDIF as input and extracts data and other channel information
encrypted in SPDIF Frame format as per IEC958 standards. Data can be transferred to
memory, using DMA support, or directly to C3 decoder without CPU intervent. SPDIF block
supports up to 2X data streams.
STA2064 System description
Doc ID 16057 Rev 3 9/19
2.6.7 AC97 controller
AC97 audio controller enables SOC to control external AC97 CODECs using SOC AMBA
interconnect. It is implemented in a way to minimize audio data handling by SOC processor
with dedicated audio DMA engine. AC97 Audio Controller supports AC97 revision 2.3
compliant audio CODECs. External interface supports one external AC97 CODEC with 6
output (3 of them can be Double Rate Audio) and 3 input channels.
2.6.8 CAN
STA2064 features one CAN module that is compliant with the CAN specification V2.0 part B
(active). The bit rate can be programmed up to 1 MBaud.
2.7 Specific functions
2.7.1 GPS
STA2064 integrates HPGPS_G2, ST’s proprietary GPS IP, which is ST’s 2nd generation
High-Sensitivity Baseband. The Baseband is fully compliant with GPS and Galileo L1/E1
signal specifications, and is optimised to maximise sensitivity for both acquisition and
tracking in difficult environments. Please refer to GPS solution specifications and software
release notes for more specific performance details.
The baseband accepts a 3-bit signal at a 4MHz IF from its companion RF chip, the
STA5630. It downconverts this to baseband and feeds it to the acquisition engines (for up to
8 satellites simultaneously) and the tracking channels (for up to 32 satellites
simultaneously).
The highly parallel correlators in the acquisition engines identify each satellite signal in time
and frequency domains, and the results are passed to the tracking channels. The tracking
channels fine-tune the lock, then track continuously, providing orbit data and timing
measurements to the ARM CPUs.
The management of the hardware for these operations, and the myriad of complex
conditions that arise, is performed in a complete GPS software library supplied by ST. This
library also takes the resultant measurement data and processes it to maintain satellite
databases and calculate the user's position, velocity and time(PVT) solutions.
The PVT solution, and other useful data, is made available to the user's application via an
API in the ST GPS library. This runs on a royalty-free real-time kernel (OS20), with ports to
industry-standard operating systems also available. In stand-alone mode, the outputs are
generated in standard NMEA message format.
Options are also available in the software library to support ST Self-Trained Assisted GPS
(ST-AGPS), a complete and scalable solution for assisting GPS start-up with Autonomous
Ephemeris prediction when no network is available, and with simple download when a
network is available followed by prediction for the following 7 days.
The GPS subsystem is based on an ARM966 processor and is clocked by two clocks:
MCLK: ARM966 CPU clock
RFCLK: 16f
0
or 32f
0
, from RF chip
MCLK is derived from the PLL2 clock with a divisor from 3 to 16, giving an ARM966
operating frequency in the range from 208 to 39 MHz, in the case the PLL2 is running at 624

STA2064N

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
RF Microcontrollers - MCU Infotainment ARM1176 533MHz 8 GPS 512Byte
Lifecycle:
New from this manufacturer.
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