Description STA2064
4/19 Doc ID 16057 Rev 3
1 Description
STA2064 is a highly integrated SOC application processor combining host capability with
high performance embedded GPS.
STA2064 targets vehicle head units and mobile navigation (PND), telematics, infotainment,
advanced audio and connectivity systems. The STA2064 provides all the elements that are
essential to build a cost effective solution.
Figure 1. Application implementation example
STA2064 System description
Doc ID 16057 Rev 3 5/19
2 System description
2.1 MCU
ARM1176-JZF advanced risc machine CPU up to 533 MHz (with Vdd greater or equal to
1.20 V and under process and temperature worst case conditions).
2.2 Embedded memories
2.2.1 Embedded SRAM (eSRAM)
The embedded SRAM is 8K x 32 (32 KB).
2.3 System functions
2.3.1 System and reset controller (SRC)
This provides a control interface for clock generation components external to the subsystem.
It also controls system-wide and peripherals-specific energy management features.
2.3.2 PMU
The power manager module controls the SLEEP to DEEP-SLEEP modes transition,
controls the external voltage switches on the Vdd and Vddio, monitors the external power
supply (via two signals, Vddok and BATOK), can force the emergency entry of the SDRAM
in self-refresh, and controls the wake-up from DEEP-SLEEP mode.
2.3.3 DMA
Direct memory access can be used with DMA peripherals. FIFO fill/empty requests from
these peripherals can be serviced immediately by the DMA Controller without CPU
interaction. Peripheral-to-peripheral and memory-to-memory DMA are also supported.
STA2064 features two DMA engines. Each DMA supports up to 8-channels and up to 32
requests.
2.3.4 Vectored interrupt controller (VIC)
The VIC allows the OS interrupt handler to quickly dispatch interrupt service routines in
response to peripheral interrupts.
2.3.5 GPIOs
Four GPIO ports provide 65 programmable inputs or outputs that can be controlled in two
modes:
software mode through an APB bus interface
hardware mode through a hardware control interface
System description STA2064
6/19 Doc ID 16057 Rev 3
2.3.6 Real-time clock (RTC)
The RTC provides a one second resolution clock. This keeps time when the system is
inactive and can be used to wake the system up when a programmed ‘alarm’ time is
reached. It has a clock trimming feature to compensate the drift of the 32.768 kHz crystal.
2.3.7 Real-time timer (RTT)
The RTT has the possibility of being clocked off. This reduces the always_on domain
consumption during Deep Sleep. By default the RTT has its clock enabled.
2.3.8 Always_ON supply
The “Always_ON” domain retains its two separate supplies, one for the core logic (V
DDON
)
and one for the IOs (V
IOON
).
The V
DDON
supply is equal to V
DD
during normal operation but, with the goal of reaching the
lowest consumption possible, can also be configured as low as 1.0 ±10%V when the device
is in deep-sleep.
2.3.9 Enhanced function timer (EFT)
STA2064 features 4 16-bit EFTs. Each of the four EFT timers has a 16-bit free-running
counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse
counter function, and a PWM channel with selectable frequency.
2.3.10 Watchdog timer (WDT)
This OS resource is used to trigger a system reset in the event of software failure.
2.4 Memory interfaces
2.4.1 SD/MMC
STA2064 features two SD/SDIO/MMC interfaces up to 52 MHz / one up to 8-bit data, the
other up to 4-bit data. The main clock available to the peripherals is:
PLL2CLK/13 (when PLL2CLK is 624 MHz and SRC_MMC52 = 0, 48 MHz will be
generated)
PLL2CLK/12 (when PLL2CLK is 624 MHz and SRC_MMC = 1, 52 MHz will be
generated)
PLL2CLK/9 (when PLL2CLK is 432 MHz, 48 MHz will be generated)
The peripheral is compliant to the following standards:
MMC 4.4
SD 2.0/Part 1 - Physical Layer
SD 2.0/Part E1 - SDIO Specification

STA2064N

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
RF Microcontrollers - MCU Infotainment ARM1176 533MHz 8 GPS 512Byte
Lifecycle:
New from this manufacturer.
Delivery:
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