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AD734ANZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
AD734
Rev. E | Page 3 of 20
SPECIFICATIONS
T
A
= +25°C, +V
S
= VP = +15 V, −V
S
= VN = −15 V, R
L
≥ 2 kΩ, unless otherwise noted.
Generalized transfer function:
(
)
(
)
()
⎪
⎭
⎪
⎬
⎫
⎪
⎩
⎪
⎨
⎧
−−
−
−−
=
21
21
2121
ZZ
UU
YYXX
AW
O
Table 1.
A B S
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
MULTIPLIER PERFORMANCE
Transfer Function W =
XY/10
W =
XY/10
W =
XY/10
Total Static Error
1
−10 V ≤ X, Y ≤ 10 V 0.1 0.4 0.1 0.25 0.1 0.4 %
Over T
MIN
to T
MAX
1 0.6 1.25 %
vs. Temperature T
MIN
to T
MAX
0.004 0.003 0.004 %/°C
vs. Either Supply ±V
S
= 14 V to 16 V 0.01 0.05 0.01 0.05 0.01 0.05 %/V
Peak Nonlinearity −10 V ≤ X ≤ +10 V,
Y = +10 V
0.05 0.05 0.05 %
−10 V ≤ Y ≤ +10 V,
X = +10 V
0.025 0.025 0.025 %
THD
2
X = 7 V rms, Y =
+10 V, f ≤ 5 kHz
−58 −66 −58 dBc
T
MIN
to T
MAX
−55 −63 −55 dBc
Y = 7 V rms, X =
+10 V, f ≤ 5 kHz
−60 −80 −60 dBc
T
MIN
to T
MAX
−57 −74 −57 dBc
Feedthrough X = 7 V rms, Y =
nulled, f ≤ 5 kHz
−85 −60 −85 −70 –85 –60 dBc
Y = 7 V rms, X =
nulled, f ≤ 5 kHz
−85 −66 −85 −76 −85 −66 dBc
Noise (RTO) X = Y = 0 V
Spectral Density 100 Hz to 1 MHz 1.0 1.0 1.0 μV/√Hz
Total Output Noise 10 Hz to 20 kHz −94 −88 −94 −88 −94 −88 dBc
T
MIN
to T
MAX
−85 −85 −85 dBc
DIVIDER PERFORMANCE
(Y = 10 V)
Transfer Function W =
XY/U
W =
XY/U
W =
XY/U
Gain Error Y = 10 V, U = 100 mV
to 10 V
1 1 1 %
X Input Clipping Level Y ≤ 10 V 1.25 × U 1.25 × U 1.25 × U V
U Input Scaling Error
3
0.3 0.15 0.3 %
T
MIN
to T
MAX
0.8 0.65 1 %
Output to 1% U = 1 V to 10 V step,
X = 1 V
100 100 100 ns
INPUT INTERFACES
(X, Y, AND Z)
3 dB Bandwidth 40 40 40 MHz
Operating Range Differential or
common mode
±12.5 ±12.5 ±12.5 V
X Input Offset Voltage 15 5 15 mV
T
MIN
to T
MAX
25 15 25 mV
Y Input Offset Voltage 10 5 10 mV
T
MIN
to T
MAX
12 6 12 mV
Z Input Offset Voltage 20 10 20 mV
T
MIN
to T
MAX
50 50 90 mV
Z Input PSRR (Either
Supply)
f ≤ 1 kHz 54 70 66 70 54 70 dB
T
MIN
to T
MAX
50 56 50 dB
AD734
Rev. E | Page 4 of 20
A B S
Parameter Conditions Min Typ Max Min Typ Max Min Typ Max Unit
CMRR f = 5 kHz 70 85 70 85 70 85 dB
Input Bias Current
(X, Y, Z Inputs)
50 300 50 150 50 300 nA
T
MIN
to T
MAX
400 300 500 nA
Input Resistance Differential 50 50 50 kΩ
Input Capacitance Differential 2 2 2 pF
DENOMINATOR INTERFACES
(U0, U1, AND U2)
Operating Range VN to
VP − 3
VN to
VP − 3
VN to
VP − 3
V
Denominator Range 1000:1 1000:1 1000:1
Interface Resistor U1 to U2 28 28 28 kΩ
OUTPUT AMPLIFIER (W)
Output Voltage Swing T
MIN
to T
MAX
±12 ±12 ±12 V
Open-Loop Voltage Gain X = Y = 0, input to Z 72 72 72 dB
Dynamic Response From X or Y input,
C
LOAD
≤ 20 pF
3 dB Bandwidth W ≤ 7 V rms 8 10 8 10 8 10 MHz
Slew Rate 450 450 450 V/μs
Settling Time +20 V or −20 V
output step
To 1% 125 125 125 ns
To 0.1% 200 200 200 ns
Short-Circuit Current T
MIN
to T
MAX
20 50 80 20 50 80 20 50 80 mA
POWER SUPPLIES, ±V
S
Operating Supply Range ±8 ±16.5 ±8 ±16.5 ±8 ±16.5 V
Quiescent Current T
MIN
to T
MAX
6 9 12 6 9 12 6 9 12 mA
1
Figures given are percent of full scale (for example, 0.01% = 1 mV).
2
dBc refers to decibels relative to the full-scale input (carrier) level of 7 V rms.
3
See for test circuit. Figure 28
AD734
Rev. E | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation
for T
J
max = 175°C 500 mW
X, Y, and Z Input Voltages VN to VP
Output Short-Circuit Duration Indefinite
Storage Temperature Range
Q-14 −65°C to +150°C
N-14 −65°C to +150°C
Operating Temperature Range
AD734A, AD734B (Industrial) −40°C to +85°C
AD734S (Military) −55°C to +125°C
Lead Temperature Range (Soldering, 60 sec) +300°C
Transistor Count 81
ESD Rating 500 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θ
JA
Unit
14-Lead PDIP (N-14) 150 °C/W
14-Lead CERDIP (Q-14) 110 °C/W
ESD CAUTION
W
12
DD
13
VP
14
X2
2
3
U0
U1
U2
X1
1
Z2
ER
VN
Y2
Y1
Z1
11
10
9
8
7
6
54
0.122
(3.0988)
0.093 (2.3622)
00827-002
Figure 2. Chip Dimensions and Bonding Diagram, Dimensions shown in inches and (mm), (Contact factory for latest dimensions)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

AD734ANZ

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