14-Bit, 125 MSPS, 1.8 V Dual
Analog-to-Digital Converter
Enhanced Product
AD9648-EP
Rev. B Document Feedback
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FEATURES
1.8 V analog supply operation
1.8 V CMOS or LVDS outputs
SNR = 74.5 dBFS at 70 MHz
SFDR = 91 dBc at 70 MHz
Low power: 106 mW/channel at 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.5 LSB at 25°C
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC
standard)
Military temperature range: −55°C to +125°C
Controlled manufacturing baseline
Qualification data available on request
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE,
CDMA20
00, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Broadband data applications
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
FUNCTIONAL BLOCK DIAGRAM
VIN+A
VIN–A
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
ORA
D0A
D13A
DCOA
DRVDD
ORB
D13B
D0B
DCOB
SDIOAGNDAVDD SCLK
SPI
PROGRAMMING DATA
MUX OPTION
PDWN DFSCLK+ CLK–
MODE
CONTROLS
DCS
DUTY CYCLE
STABILIZER
SYNC
DIVIDE
1 TO 8
OEB
CSB
REF
SELECT
ADC
CMOS/LVDS
OUTPUT BUFFER
ADC
CMOS/LVDS
OUTPUT BUFFER
AD9648-EP
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE F
IGURE 7 FOR LVDS PIN NAMES.
13386-001
F
igure 1.
PRODUCT HIGHLIGHTS
1. The AD9648-EP operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V CMOS or LVDS logic families.
2. The sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use
.
3. A
standard serial port interface supports various produc
t
f
eatures and functions, such as data output formattin
g,
i
nternal clock divider, power-down, DCO/data timing an
d
o
ffset adjustments.
4. The AD9648-EP is packaged in a 64-lead, RoHS-compliant
LFCSP that is pin-compatible with the AD9650/AD9269/
AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9628/
AD9231 12-bit ADCs, and the AD9608/AD9204 10-bit
ADCs, enabling a simple migration path between 10-bit
and 16-bit converters sampling from 20 MSPS to 125 MSPS.
AD9648-EP Enhanced Product
Rev. B | Page 2 of 17
TABLE OF CONTENTS
Features .............................................................................................. 1
Enhanced Product Features ............................................................ 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
DC Specifications ........................................................................... 4
AC Specifications ........................................................................... 5
Digital Specifications ....................................................................6
Switching Specifications .................................................................7
Timing Specifications ...................................................................8
Absolute Maximum Ratings ......................................................... 10
Thermal Characteristics ............................................................ 10
ESD Caution................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
1/16Rev. A to Rev. B
Change to Product Highlights Section .......................................... 1
Changes to General Description Section ...................................... 3
Change to Differential Nonlinearity (DNL) Parameter,
Table 1 ................................................................................................ 4
Changes to Signal-to-Noise-Ratio (SNR) Parameter, Signal-to-
Noise and Distortion (SINAD) Parameter, and Worst Other
(Harmonic or Spur) Parameter, Table 2 ........................................ 5
Changes to Table 6 .......................................................................... 10
12/15Rev. 0 to Rev. A
Changes to Figure 3 ........................................................................... 8
Changes to Figure 4 ........................................................................... 9
9/15Revision 0: Initial Version
Enhanced Product AD9648-EP
Rev. B | Page 3 of 17
GENERAL DESCRIPTION
The AD9648-EP is a monolithic, dual-channel, 1.8 V supply,
14-bit, 125 MSPS analog-to-digital converter (ADC). It features
a high performance sample-and-hold circuit and on-chip
voltage reference.
The product uses multistage differential pipeline architecture
with output error correction logic to provide 14-bit accuracy at
125 MSPS data rates and to guarantee no missing codes over the
full operating temperature range.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom
user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles.
An optional duty cycle stabilizer (DCS) compensates for wide
variations in the clock duty cycle while maintaining excellent
overall ADC performance.
The digital output data is presented in offset binary, Gray code, or
twos complement format. A data output clock (DCO) is provided
for each ADC channel to ensure proper latch timing with receiving
logic. Output logic levels of 1.8 V CMOS or LVDS are supported.
Output data can also be multiplexed onto a single output bus.
The AD9648-EP is available in a 64-lead RoHS-compliant LFCSP
and is specified over the −55°C to +125°C temperature range.
Additional information, including Typical Performance
Characteristics at 125 MSPS, can be found in the AD9648 data
sheet.

AD9648TCPZ125EPRL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 14Bit125MSPS Dual 1.8V ADCParallelLVDS
Lifecycle:
New from this manufacturer.
Delivery:
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