OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD9648TCPZ125EPRL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
AD9648-EP Enhanced Product
Rev. B | Page 4 of 17
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.
Table 1.
Parameter Temperature Min Typ Max Unit
RESOLUTION Full 14 Bits
ACCURACY
No Missing Codes Full Guaranteed
Offset Error Full −0.8 −0.3 +0.2 % FSR
Gain Error Full −6.3 ±1.3 +6.3 % FSR
Differential Nonlinearity (DNL)
1
Full −0.7 +1.3 LSB
25°C ±0.5 LSB
Integral Nonlinearity (INL)
1
Full −2.6 +2.6 LSB
25°C ±1.0 LSB
MATCHING CHARACTERISTIC
Offset Error Full ±0.01 ±0.8 % FSR
Gain Error Full ±0.5 ±7.0 % FSR
TEMPERATURE DRIFT
Offset Error Full ±2 ppm/°C
Gain Error Full ±50 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode) Full 0.98 1.00 1.02 V
Load Regulation Error at 1.0 mA Full 2 mV
INPUT REFERRED NOISE
VREF = 1.0 V 25°C 0.98 LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V Full 2 V p-p
Input Capacitance
2
Full 5 pF
Input Resistance (Differential) Full 7.5 kΩ
Input Common-Mode Voltage Full 0.9 V
Input Common-Mode Range Full 0.5 1.3 V
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 1.9 V
Supply Current
I
AVDD
1
Full 95 100 mA
I
DRVDD
(1.8 V CMOS)
1
Full 22.5 23.8 mA
I
DRVDD
(1.8 V LVDS)
1
Full 65.0 66.4 mA
POWER CONSUMPTION
DC Input Full 155.5 mW
Sine Wave Input (DRVDD = 1.8 V CMOS Output Mode) Full 211.5 223 mW
Sine Wave Input (DRVDD = 1.8 V LVDS Output Mode) Full 288 300 mW
Standby Power
3
Full 120 mW
Power-Down Power Full 2.0 mW
1
Measure with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode).
Enhanced Product AD9648-EP
Rev. B | Page 5 of 17
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.
Table 2.
Parameter
1
Temperature Min Typ Max Unit
SIGNAL-TO-NOISE-RATIO (SNR)
f
IN
= 9.7 MHz 25°C 75.0 dBFS
f
IN
= 30.5 MHz 25°C 74.7 dBFS
f
IN
= 70 MHz 25°C 74.5 dBFS
Full 72.5 dBFS
f
IN
= 100 MHz
25°C 73.9 dBFS
f
IN
= 200 MHz 25°C 71.5 dBFS
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
f
IN
= 9.7 MHz 25°C 73.9 dBFS
f
IN
= 30.5 MHz 25°C 73.4 dBFS
f
IN
= 70 MHz 25°C 73.3 dBFS
Full 72.3 dBFS
f
IN
= 100 MHz 25°C 72.8 dBFS
f
IN
= 200 MHz 25°C 70.3 dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
f
IN
= 9.7 MHz 25°C 12 Bits
f
IN
= 30.5 MHz 25°C 11.9 Bits
f
IN
= 70 MHz Full 11.8 11.9 Bits
f
IN
= 100 MHz 25°C 11.8 Bits
f
IN
= 200 MHz 25°C 11.4 Bits
WORST SECOND OR THIRD HARMONIC
f
IN
= 9.7 MHz 25°C −96 dBc
f
IN
= 30.5 MHz 25°C −90 dBc
f
IN
= 70 MHz 25°C −91 dBc
Full −82 dBc
f
IN
= 100 MHz 25°C −90 dBc
f
IN
= 200 MHz 25°C −84 dBc
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
f
IN
= 9.7 MHz 25°C 96 dBc
f
IN
= 30.5 MHz 25°C 90 dBc
f
IN
= 70 MHz 25°C 91 dBc
Full 82 dBc
f
IN
= 100 MHz
25°C
90
dBc
f
IN
= 200 MHz 25°C 84 dBc
WORST OTHER (HARMONIC OR SPUR)
f
IN
= 9.7 MHz 25°C −97 dBc
f
IN
= 30.5 MHz 25°C −97 dBc
f
IN
= 70 MHz 25°C −97 dBc
Full −89 dBc
f
IN
= 100 MHz 25°C −92 dBc
f
IN
= 200 MHz 25°C −90 dBc
TWO-TONE SFDR
f
IN
= 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) 25°C 84 dBc
CROSSTALK
2
Full −95 dB
ANALOG INPUT BANDWIDTH 25°C 650 MHz
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
AD9648-EP Enhanced Product
Rev. B | Page 6 of 17
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless
otherwise noted.
Table 3.
Parameter Temperature Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Internal Common-Mode Bias Full 0.9 V
Differential Input Voltage Full 0.3 3.6 V p-p
Input Voltage Range Full AGND − 0.3 AVDD + 0.2 V
Input Common-Mode Range Full 0.9 1.4 V
High Level Input Current Full −10 +10 µA
Low Level Input Current Full −10 +10 µA
Input Capacitance Full 4 pF
Input Resistance Full 8 10 12 kΩ
LOGIC INPUT (CSB)
1
High Level Input Voltage Full 1.22 DRVDD + 0.2 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −10 +10 µA
Low Level Input Current Full 40 132 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT (SCLK/DFS/SYNC)
2
High Level Input Voltage Full 1.22 DRVDD + 0.2 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current (VIN = 1.8 V) Full −92 −135 µA
Low Level Input Current
Full
−10
+10
µA
Input Resistance Full 26 kΩ
Input Capacitance Full 2 pF
LOGIC INPUT/OUTPUT (SDIO/DCS)
1
High Level Input Voltage Full 1.22 DRVDD + 0.2 V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current Full −10 +10 µA
Low Level Input Current Full 38 128 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
LOGIC INPUTS (OEB, PDWN)
2
High Level Input Voltage
Full
1.22
DRVDD + 0.2
V
Low Level Input Voltage Full 0 0.6 V
High Level Input Current (VIN = 1.8 V) Full −90 −134 µA
Low Level Input Current Full −10 +10 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD9648TCPZ125EPRL7

Mfr. #:
Buy AD9648TCPZ125EPRL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 14Bit125MSPS Dual 1.8V ADCParallelLVDS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet