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AD9648TCPZ125EPRL7

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
Enhanced Product AD9648-EP
Rev. B | Page 13 of 17
D4–
D4+
DRVDD
D5–
D5+
D6–
D6+
DCO–
DCO+
D7–
D7+
DRVDD
D8–
D8+
D9–
D9+
AVDD
AVDD
VIN+B
VIN–B
AVDD
AVDD
RBIAS
VCM
SENSE
VREF
AVDD
AVDD
VIN–A
VIN+A
AVDD
AVDD
CLK+
CLK–
SYNC
NC
NC
NC
NC
D0– (LSB)
D0+ (LSB)
DRVDD
D1–
D1+
D2–
D2+
D3–
D3+
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
OR+
OR–
D13+ (MSB)
D13– (MSB)
D12+
D12–
DRVDD
D11+
D11–
D10+
D10–
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE DEVICE. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
13386-007
AD9648-EP
INTERLEAVED PARALLEL LVDS
TOP VIEW
(Not to Scale)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Figure 7. Interleaved Parallel LVDS Pin Configuration (Top View)
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
10, 19, 28, 37 DRVDD Supply Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54,
59, 60, 63, 64
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
4, 5, 6, 7 NC No Connect. Do not connect to these pins.
0 AGND,
Exposed Pad
Ground The exposed thermal pad on the bottom of the package provides the analog ground for
the device. This exposed pad must be connected to ground for proper operation.
ADC Analog
51 VIN+A Input Differential Analog Input Pin (+) for Channel A.
52 VIN−A Input Differential Analog Input Pin (−) for Channel A.
62 VIN+B Input Differential Analog Input Pin (+) for Channel B.
61 VIN−B Input Differential Analog Input Pin (−) for Channel B.
55 VREF Input/Output Voltage Reference Input/Output.
56 SENSE Input Reference Mode Selection.
58 RBIAS Input/Output External Reference Bias Resistor. Connect to a 10 kΩ (1% tolerance) resistor to ground.
57 VCM Output Common-Mode Level Bias Output for Analog Inputs.
1
CLK+
Input
ADC Clock Input—True.
2 CLK− Input ADC Clock Input—Complement.
Digital Input
3 SYNC Input Digital Synchronization Pin. Slave mode only.
AD9648-EP Enhanced Product
Rev. B | Page 14 of 17
Pin No. Mnemonic Type Description
Digital Outputs
9
D0+ (LSB)
Output
Channel A/Channel B LVDS Output Data 0—True.
8 D0− (LSB) Output Channel A/Channel B LVDS Output Data 0—Complement.
12 D1+ Output Channel A/Channel B LVDS Output Data 1—True.
11 D1− Output Channel A/Channel B LVDS Output Data 1—Complement.
14 D2+ Output Channel A/Channel B LVDS Output Data 2—True.
13 D2− Output Channel A/Channel B LVDS Output Data 2—Complement.
16 D3+ Output Channel A/Channel B LVDS Output Data 3—True.
15 D3− Output Channel A/Channel B LVDS Output Data 3—Complement.
18 D4+ Output Channel A/Channel B LVDS Output Data 4—True.
17 D4− Output Channel A/Channel B LVDS Output Data 4—Complement.
21 D5+ Output Channel A/Channel B LVDS Output Data 5—True.
20 D5− Output Channel A/Channel B LVDS Output Data 5—Complement.
23
D6+
Output
Channel A/Channel B LVDS Output Data 6—True.
22 D6− Output Channel A/Channel B LVDS Output Data 6—Complement.
27 D7+ Output Channel A/Channel B LVDS Output Data 7—True.
26 D7− Output Channel A/Channel B LVDS Output Data 7—Complement.
30 D8+ Output Channel A/Channel B LVDS Output Data 8—True.
29
D8−
Output
Channel A/Channel B LVDS Output Data 8—Complement.
32 D9+ Output Channel A/Channel B LVDS Output Data 9—True.
31 D9− Output Channel A/Channel B LVDS Output Data 9—Complement.
34 D10+ Output Channel A/Channel B LVDS Output Data 10—True.
33 D10− Output Channel A/Channel B LVDS Output Data 10—Complement.
36 D11+ Output Channel A/Channel B LVDS Output Data 11—True.
35 D11− Output Channel A/Channel B LVDS Output Data 11—Complement.
39 D12+ Output Channel A/Channel B LVDS Output Data 12—True.
38 D12− Output Channel A/Channel B LVDS Output Data 12—Complement.
41 D13+ (MSB) Output Channel A/Channel B LVDS Output Data 13—True.
40 D13− (MSB) Output Channel A/Channel B LVDS Output Data 13—Complement.
43 OR+ Output Channel A/Channel B LVDS Overrange Output—True.
42 OR− Output Channel A/Channel B LVDS Overrange Output—Complement.
25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True.
24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement.
SPI Control
45 SCLK/DFS Input SPI Serial Clock/Data Format Select Pin in External Pin Mode.
44 SDIO/DCS Input/Output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
46
CSB
Input
SPI Chip Select (Active Low).
ADC Configuration
47 OEB Input Output Enable Input (Active Low).
48 PDWN Input Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as
power-down or standby.
Enhanced Product AD9648-EP
Rev. B | Page 15 of 17
B D9–/D8–
B D9+/D8+
DRVDD
B D11–/D10–
B D11+/D10+
B D13–/D12– (MSB)
B D13+/D12+ (MSB)
DCO–
DCO+
A D1–/D0– (LSB)
A D1+/D0+ (LSB)
DRVDD
A D3–/D2–
A D3+/D2+
A D5–/D4–
A D5+/D4+
AVDD
AVDD
VIN+B
VIN–B
AVDD
AVDD
RBIAS
VCM
SENSE
VREF
AVDD
AVDD
VIN–A
VIN+A
AVDD
AVDD
CLK+
CLK–
SYNC
NC
NC
NC
NC
B D1–/D0– (LSB)
B D1+/D0+ (LSB)
DRVDD
B D3–/D2–
B D3+/D2+
B D5–/D4–
B D5+/D4+
B D7–/D6–
B D7+/D6+
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
OR+
OR–
A D13+/D12+ (MSB)
A D13–/D12– (MSB)
A D11+/D10+
A D11–/D10–
DRVDD
A D9+/D8+
A D9–/D8–
A D7+/D6+
A D7–/D6–
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE DEVICE. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
13386-008
AD9648-EP
CHANNEL MULTIPLEXED LVDS
TOP VIEW
(Not to Scale)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Figure 8. Channel Multiplexed LVDS Pin Configuration (Top View)
Table 10 Pin Function Descriptions (Channel Multiplexed Parallel LVDS Mode)
Pin No. Mnemonic Type Description
ADC Power Supplies
10, 19, 28, 37
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54,
59, 60, 63, 64
AVDD Supply Analog Power Supply (1.8 V Nominal).
4, 5, 6, 7 NC Do Not Connect.
0 AGND, Exposed Pad Ground The exposed thermal pad on the bottom of the package provides the analog
ground for the device. This exposed pad must be connected to ground for proper
operation.
ADC Analog
51 VIN+A Input Differential Analog Input Pin (+) for Channel A.
52 VIN−A Input Differential Analog Input Pin (−) for Channel A.
62
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
61 VIN−B Input Differential Analog Input Pin (−) for Channel B.
55 VREF Input/Output Voltage Reference Input/Output.
56 SENSE Input Reference Mode Selection.
58 RBIAS Input/Output External Reference Bias Resistor. Connect to a 10 kΩ (1% tolerance) resistor to
ground.
57 VCM Output Common-Mode Level Bias Output for Analog Inputs.
1 CLK+ Input ADC Clock Input—True.
2 CLK− Input ADC Clock Input—Complement.
Digital Input
3
SYNC
Input
Digital Synchronization Pin. Slave mode only.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

AD9648TCPZ125EPRL7

Mfr. #:
Buy AD9648TCPZ125EPRL7
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 14Bit125MSPS Dual 1.8V ADCParallelLVDS
Lifecycle:
New from this manufacturer.
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