AD9648-EP Enhanced Product
Rev. B | Page 10 of 17
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Electrical
AVDD to AGND −0.3 V to +2.0 V
DRVDD to AGND −0.3 V to +2.0 V
VIN+A/VIN+B, VIN−A/VIN−B to AGND −0.3 V to AVDD + 0.2 V
CLK+, CLK− to AGND −0.3 V to AVDD + 0.2 V
SYNC to DRVDD −0.3 V to AVDD + 0.2 V
VCM to AGND −0.3 V to AVDD + 0.2 V
RBIAS to AGND −0.3 V to AVDD + 0.2 V
CSB to AGND −0.3 V to DRVDD + 0.2 V
SCLK/DFS to AGND −0.3 V to DRVDD + 0.2 V
OEB −0.3 V to DRVDD + 0.2 V
PDWN −0.3 V to DRVDD + 0.2 V
D0A/D0B through D13A/D13B to
AGND
−0.3 V to DRVDD + 0.2 V
DCOA/DCOB to AGND
−0.3 V to DRVDD + 0.2 V
Environmental
Operating Temperature Range
(Ambient)
−55°C to +125°C
Maximum Junction Temperature
Under Bias
150°C
Storage Temperature Range
(Ambient)
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL CHARACTERISTICS
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the printed
circuit board (PCB) increases the reliability of the solder joints
and maximizes the thermal capability of the package.
Table 7. Thermal Resistance
Package Type
Velocity
(m/sec)
θ
1, 2
θ
1, 3
θ
1, 4
1,2
Unit
64-Lead LFCSP
9 mm × 9 mm
(CP-64-4)
0 22.3 1.4 11.8 0.1 °C/W
1.0 19.5 N/A N/A 0.2 °C/W
2.5 17.5 N/A N/A 0.2 °C/W
1
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
2
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
Typical θ
JA
is specified for a 4-layer PCB with a solid ground
plane. As shown Table 7, airflow improves heat dissipation,
which reduces θ
JA
. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes reduces θ
JA
.
ESD CAUTION
