83026BMI-01LFT Datasheet 83026BGI-01LFT, 83026BGI-01LF, 83026BMI-01LF | P10-P12

83026I-01 Data Sheet

FIGURE 2C. CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 2B. CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER

FIGURE 2D. CLK/nCLK INPUT DRIVEN BY

3.3V LVDS DRIVER

3.3V

Zo = 50 Ohm

LVPECL

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

3.3V

Input

Zo = 50 Ohm

Input

HiPerClockS

CLK

nCLK

3.3V

125

Zo = 50 Ohm

3.3V

125

LVPECL

3.3V

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL

and other differential signals. Both V

SWING

and V

must meet

the V

and V

CMR

input requirements. Figures 2A to 2E show

interface examples for the CLK/nCLK input driven by the most

common driver types. The input interfaces suggested here are

FIGURE 2A. CLK/nCLK INPUT DRIVEN BY

LVHSTL DRIVER

examples only. Please consult with the vendor of the driver

component to conﬁ rm the driver termination requirements.

For example in Figure 2A, the input termination applies for

LVHSTL drivers. If you are using an LVHSTL driver from another

vendor, use their termination recommendation.

1.8V

Input

LVHSTL Driver

ICS

HiPerClockS

LVHSTL

3.3V

Zo = 50 Ohm

HiPerClockS

CLK

nCLK

FIGURE 2E. CLK/nCLK INPUT DRIVEN BY

3.3V LVPECL DRIVER WITH AC COUPLE

Zo = 50 Ohm

125

HiPerClockS

CLK

nCLK

3.3V

100 - 200

3.3V

100 - 200

Input

R5,R6 locate near the driver pin.

Zo = 50 Ohm

125

LVPECL

Zo = 50 Ohm

100

3.3V

LVDS_Driv er

Zo = 50 Ohm

Receiv er

CLK

nCLK

3.3V

83026I-01 Data Sheet

SCHEMATIC EXAMPLE

Figure 3 shows an application schematic example of 83026I-01.

The 83026I-01 CLK/nCLK input can directly accepts various

types of differential signal. In this example, the input is driven by

an LVDS driver. The 83026I-01 outputs are LVCMOS drivers. In

VDDO

R1 43

LVDS

VDD

100

VDD=3.3V

LVCMOS

Zo = 50 Ohm

0.1u

3.3V

Zo = 50 Ohm

VDDO= 3.3V, 2.5V or 1.8V

Zo = 50 Ohm

U1 ICS83026I-01

VDD

CLK

nCLK

VDDO

GND

LVCMOS

R2 43

0.1u

VDD

Zo = 50 Ohm

FIGURE 3. 83026I-01 SCHEMATIC EXAMPLE

this example, series termination approach is shown. Additional

termination approaches are shown in the LVCMOS Termination

Application Note.

TRANSISTOR COUNT

The transistor count for ICS83026I-0I is: 260

TABLE 5A. θ

VS. AIR FLOW TABLE FOR 8 LEAD SOIC

by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 153.3°C/W 128.5°C/W 115.5°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 112.7°C/W 103.3°C/W 97.1°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

RELIABILITY INFORMATION

TABLE5B. θ

VS. AIR FLOW TABLE FOR 8 LEAD TSSOP

by Velocity (Linear Feet per Minute)

0 200 500

Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

83026I-01 Data Sheet

TABLE 6A. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MS-012

PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC

SYMBOL

Millimeters

MINIMUM MAXIMUM

A 1.35 1.75

A1 0.10 0.25

B 0.33 0.51

C 0.19 0.25

D 4.80 5.00

E 3.80 4.00

e 1.27 BASIC

H 5.80 6.20

h 0.25 0.50

L 0.40 1.27

0° 8°

PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP

TABLE 6B. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

SYMBOL

Millimeters

Minimum Maximum

A -- 1.20

A1 0.05 0.15

A2 0.80 1.05

b 0.19 0.30

c 0.09 0.20

D 2.90 3.10

E 6.40 BASIC

E1 4.30 4.50

e 0.65 BASIC

L 0.45 0.75

0° 8°

aaa -- 0.10

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

83026BMI-01LFT

Mfr. #:

Buy 83026BMI-01LFT

Manufacturer:

IDT

Description:

Clock Buffer 1-to-2 Differential to LVCMOS Fanout Buf

Lifecycle:

New from this manufacturer.

Delivery:

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83026BMI-01LFT

83026BMI-01LFT

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