83026BMI-01LFT Datasheet 83026BGI-01LFT, 83026BGI-01LF, 83026BMI-01LF | P4-P6

83026I-01 Data Sheet

TABLE 4A. AC CHARACTERISTICS, V

= 3.3V ± 5%, V

DDO

= 3.3V ± 5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

MAX

Output Frequency 350 MHz

Propagation Delay; NOTE 1

ƒ ≤ 350MHz

1.3 1.9 2.5 ns

tsk(o) Output Skew; NOTE 2, 4 15 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 900 ps

tjit

Buffer Additive Phase Jitter, RMS, refer to

Additive Phase Jitter Section

0.03 ps

/ t

Output Rise/Fall Time 20% to 80% 150 800 ps

odc Output Duty Cycle

ƒ ≤ 66MHz

48 52 %

67MHz ≤ ƒ ≤ 166MHz

45 55 %

167MHz ≤ ƒ ≤ 350MHz

40 60 %

NOTE 1: Measured from the differential input crossing point to V

DDO

/2 of the output.

NOTE 2: Deﬁ ned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at V

DDO

/2.

NOTE 3: Deﬁ ned as skew between outputs on different devices operating at the same supply voltages and with

equal load conditions. Using the same type of inputs on each device, the outputs are measured at V

DDO

/2.

NOTE 4: This parameter is deﬁ ned in accordance with JEDEC Standard 6.

TABLE 3D. DIFFERENTIAL DC CHARACTERISTICS, V

= 3.3V ± 5%, V

DDO

= 1.71V TO 3.465V, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

Input High Current

nCLK V

= V

= 3.465V 150 µA

CLK V

= V

= 3.465V 150 µA

Input Low Current

nCLK V

= 0V, V

= 3.465V -150 µA

CLK V

= 0V, V

= 3.465V -5 µA

Peak-to-Peak Input Voltage; NOTE 1 0.15 1.3 V

CMR

Common Mode Input Voltage; NOTE 2, 3 GND + 0.5 V

- 0.85 V

NOTE 1: V

can exceed 1.3V provided that there is sufﬁ cient offset level to keep V

> 0V.

NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V

+ 0.3V.

NOTE 3: Common mode voltage is deﬁ ned as V

83026I-01 Data Sheet

TABLE 4B. AC CHARACTERISTICS, V

= 3.3V ± 5%, V

DDO

= 2.5V ± 5%, TA = -40°C TO 85°C

TABLE 4C. AC CHARACTERISTICS, V

= 3.3V ± 5%, V

DDO

= 1.8V ± 5%, TA = -40°C TO 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

MAX

Output Frequency 350 MHz

Propagation Delay; NOTE 1

ƒ ≤ 350MHz

1.5 2.0 2.6 ns

tsk(o) Output Skew; NOTE 2, 4 15 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 750 ps

tjit

Buffer Additive Phase Jitter,

RMS, refer to Additive Phase

Jitter Section

0.03 ps

/ t

Output Rise/Fall Time 20% to 80% 150 800 ps

odc Output Duty Cycle

ƒ ≤ 66MHz

48 52 %

67MHz ≤ ƒ ≤ 166MHz

46 54 %

167MHz ≤ ƒ ≤ 350MHz

40 60 %

NOTE 1: Measured from the differential input crossing point to V

DDO

/2 of the output.

NOTE 2: Deﬁ ned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at V

DDO

/2.

NOTE 3: Deﬁ ned as skew between outputs on different devices operating at the same supply voltages and with

equal load conditions. Using the same type of inputs on each device, the outputs are measured at V

DDO

/2.

NOTE 4: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

MAX

Output Frequency 350 MHz

Propagation Delay; NOTE 1

ƒ ≤ 350MHz

1.9 2.5 3.1 ns

tsk(o) Output Skew; NOTE 2, 4 15 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 600 ps

tjit

Buffer Additive Phase Jitter,

RMS, refer to Additive Phase

Jitter Section

0.03 ps

/ t

Output Rise/Fall Time 20% to 80% 200 900 ps

odc Output Duty Cycle

ƒ ≤ 66MHz

48 52 %

67MHz ≤ ƒ ≤ 166MHz

43 57 %

167MHz ≤ ƒ ≤ 350MHz

40 60 %

NOTE 1: Measured from the differential input crossing point to V

DDO

/2 of the output.

NOTE 2: Deﬁ ned as skew between outputs at the same supply voltage and with equal load conditions.

Measured at V

DDO

/2.

NOTE 3: Deﬁ ned as skew between outputs on different devices operating at the same supply voltages and with

equal load conditions. Using the same type of inputs on each device, the outputs are measured at V

DDO

/2.

NOTE 4: This parameter is deﬁ ned in accordance with JEDEC Standard 65.

83026I-01 Data Sheet

ADDITIVE PHASE JITTER

Input/Output Additive

Phase Jitter at 155.52MHz

= 0.03ps typical

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

1k 10k 100k 1M 10M 100M

The spectral purity in a band at a speciﬁ c offset from the fun-

damental compared to the power of the fundamental is called

the dBc Phase Noise. This value is normally expressed using

a Phase noise plot and is most often the speciﬁ ed plot in many

applications. Phase noise is deﬁ ned as the ratio of the noise

power present in a 1Hz band at a speciﬁ ed offset from the fun-

damental frequency to the power value of the fundamental. This

ratio is expressed in decibels (dBm) or a ratio of the power in the

As with most timing speciﬁ cations, phase noise measurements

have issues. The primary issue relates to the limitations of the

equipment. Often the noise ﬂ oor of the equipment is higher

than the noise ﬂ oor of the device. This is illustrated above. The

1Hz band to the power in the fundamental. When the required

offset is speciﬁ ed, the phase noise is called a dBc value, which

simply means dBm at a speciﬁ ed offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the

entire time record of the signal. It is mathematically possible to

calculate an expected bit error rate given a phase noise plot.

device meets the noise ﬂ oor of what is shown, but can actually

be lower. The phase noise is dependant on the input source and

measurement equipment.

OFFSET FROM CARRIER FREQUENCY (HZ)

SSB PHASE NOISE dBc/HZ

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

83026BMI-01LFT

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Manufacturer:

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Description:

Clock Buffer 1-to-2 Differential to LVCMOS Fanout Buf

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83026BMI-01LFT

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