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X9523V20I-B

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
10
FN8209.2
August 31, 2010
It should be noted that when reading out the data byte for
DCP1 (100 Tap), the upper most significant bit is an
“unknown”. For DCP2 (256 Tap) however, all bits of the
data byte are relevant (See Figure 10).
CONTROL AND STATUS REGISTER
The Control and Status (CONSTAT) Register pro-
vides the user with a mechanism for changing and
reading the status of various parameters of the
X9523 (See Figure 12).
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CON-
STAT register retain their stored values even when
V1/Vcc is powered down, then powered back up. The
volatile bits however, will always power-up to a known
logic state “0” (irrespective of their value at power-down).
A detailed description of the function of each of the CON-
STAT register bits follows:
WEL: Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the
entire X9523 device. This bit must first be enabled before
ANY write operation (to DCPs, or the CONSTAT regis-
ter). If the WEL bit is not first enabled, then ANY pro-
ceeding (volatile or nonvolatile) write operation to DCPs
or the CONSTAT register, is aborted and no ACKNOWL-
EDGE is issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state. The WEL bit is enabled / set by
writing 00000010 to the CONSTAT register. Once
enabled, the WEL bit remains set to “1” until either it is
reset to “0” (by writing 00000000 to the CONSTAT regis-
ter) or until the X9523 powers down, and then up again.
Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for
another operation immediately after a STOP condition is
executed in the CONSTAT Write command sequence
(See Figure 13).
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9523. Therefore, in order to write
to any of the bits of the CONSTAT Register (except
WEL), the RWEL bit must first be set to “1”. The RWEL
bit is a volatile bit that powers up in the disabled, LOW
(“0”) state.
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT
Register Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of two cases:
—After a successful write operation to any bits of
the CONSTAT register has been completed (See
Figure 13).
—When the X9523 is powered down.
DWLK: DCP Write Lock bit - (Nonvolatile)
The DCP Write Lock bit (DWLK) is used to inhibit a DCP
write operation (changing the “wiper position”).
When the DCP Write Lock bit of the CONSTAT register
is set to “1”, then the “wiper position” of the DCPs can-
not be changed - i.e. DCP write operations cannot be
conducted:
The factory default setting for this bit is DWLK = 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9523 is active (HIGH), then nonvolatile write operations
to the DCPs are inhibited, irrespective of the DCP Write
Lock bit setting (See "WP: Write Protection Pin").
Bit(s) Description
POR1 Power-on Reset bit
V2OS V2 Output Status flag
V1OS V1 Output Status flag
CS4 Always set to “0” (RESERVED)
DWLK Sets the DCP Write Lock
RWEL Register Write Enable Latch bit
WEL Write Enable Latch bit
POR0 Power-on Reset bit
POR1
WEL
POR0
CS5
CS6CS7 CS4
CS3
CS2 CS1 CS0
V3OS
V2OS
DWLK
0
RWEL
Figure 12. CONSTAT Register Format
NV
NV
NV
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
DWLK DCP Write Operation Permissible
0 YES (Default)
1NO
X9523
11
FN8209.2
August 31, 2010
POR1, POR0: Power-on Reset bits - (Nonvolatile)
Applying voltage to V
CC
activates the Power-on Reset
circuit which holds V1RO output HIGH, until the supply
voltage stabilizes above the V
TRIP1
threshold for a
period of time, t
PURST
(See Figure 25).
The Power-on Reset bits, POR1 and POR0 of the
CONSTAT register determine the tPURST delay time of
the Power-on Reset circuitry (See "VOLTAGE MONI-
TORING FUNCTIONS"). These bits of the CONSTAT
register are nonvolatile, and therefore power-up to the
last written state.
The nominal Power-on Reset delay time can be selected
from the following table, by writing the appropriate bits to
the CONSTAT register:
The default for these bits are POR1 = 0, POR0 = 1.
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.
At power-up the VxOS (x = 2,3) bits default to the value
“0”. These bits can be set to a “1” by writing the appropri-
ate value to the CONSTAT register. To provide consis-
tency between the VxRO and VxOS however, the status
of the VxOS bits can only be set to a “1” when the corre-
sponding VxRO output is HIGH.
Once the VxOS bits have been set to “1”, they will be
reset to “0” if:
—The device is powered down, then back up,
—The corresponding VxRO output becomes LOW.
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT regis-
ter requires an Address Byte which must be set to FFh.
Only one data byte is allowed to be written for each
CONSTAT register Write operation. The user must issue
a STOP, after sending this byte to the register, to initiate
the nonvolatile cycle that stores the DWLK, POR1 and
POR0 bits. The X9523 will not ACKNOWLEDGE any
data bytes written after the first byte is entered (Refer to
Figure 13.).
When writing to the CONSTAT register, the bit CS4 must
always be set to “0”. Writing a “1” to bit CS4 of the CON-
STAT register is a reserved operation.
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).
—Write a 06H to the CONSTAT Register to set the Reg-
ister Write Enable Latch (RWEL) AND the WEL bit.
This is also a volatile cycle. The zeros in the data byte
are required. (Operation preceded by a START and
ended with a STOP).
POR1 POR0
Power-on Reset delay (t
PUV1RO
)
0 0 50ms
0 1 100ms (Default)
1 0 200ms
1 1 300ms
S
T
A
R
T
1 010010R/W
A
C
K
11111
1
11 A
C
K
SCL
SDA
S
T
O
P
A
C
K
CS7 CS6
CS5 CS4 CS3
CS2 CS1
CS0
SLAVE ADDRESS BYTE
ADDRESS BYTE
CONSTAT REGISTER DATA IN
Figure 13. CONSTAT Register Write Command Sequence
X9523
12
FN8209.2
August 31, 2010
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as qxyst01r in binary,
where xy are the Voltage Monitor Output Status
(V2OS and V3OS) bits, t is the DCP Write Lock
(DWLK) bit, and qr are the Power-on Reset delay time
(t
PUV1RO
) control bits (POR1 - POR0). This operation
is proceeded by a START and ended with a STOP bit.
Since this is a nonvolatile write cycle, it will typically
take 5ms to complete. The RWEL bit is reset by this
cycle and the sequence must be repeated to change
the nonvolatile bits again. If bit 2 is set to ‘1’ in this third
step (qxys t11r) then the RWEL bit is set, but the
V2OS, V3OS, POR1, POR0, and DWLK bits remain
unchanged. Writing a second byte to the control regis-
ter is not allowed. Doing so aborts the write operation
and the X9523 does not return an ACKNOWLEDGE.
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset all
of the nonvolatile bits in the CONSTAT Register to “0”.
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect
pin of the X9523 is active (HIGH) (See "WP: Write Pro-
tection Pin").
Figure 14. CONSTAT Register Read Command Sequence
0
Slave
Address
Address
Byte
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data
A
C
K
1
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
0 1 0 0 1 011 0 1 0 0 1 0
WRITE Operation
“Dummy” Write
READ Operation
CS7 … CS0
X9523
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

X9523V20I-B

Mfr. #:
Buy X9523V20I-B
Manufacturer:
Renesas / Intersil
Description:
IC DUAL DCP LASER CNTRL 20TSSOP
Lifecycle:
New from this manufacturer.
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