7
FN8209.2
August 31, 2010
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
before break” sequence is used internally for the FET
switches when the wiper is moved from one tap position
to another.
Hot Pluggability
Figure 7 shows a typical waveform that the X9523 might
experience in a Hot Pluggable situation. On power-up,
V1 / Vcc applied to the X9523 may exhibit some amount
of ringing, before it settles to the required value.
The device is designed such that the wiper terminal
(R
Wx
) is recalled to the correct position (as per the last
stored in the DCP NVM), when the voltage applied to
V1/Vcc exceeds V
TRIP1
for a time exceeding t
purst
(the
Power-on Reset time, set in the CONSTAT Register -
See “CONTROL AND STATUS REGISTER” on
page 10.).
Therefore, if
t
trans
is defined as the time taken for V1 /
Vcc to settle above V
TRIP1
(Figure 7): then the desired
wiper terminal position is recalled by (a maximum) time:
t
trans
+ t
purst
. It should be noted that t
trans
is determined
by system hot plug conditions.
DCP Operations
In total there are three operations that can be performed
on any internal DCP structure:
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after V1/Vcc of
the X9523 is powered down and then powered back up.
A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
WCR only. The contents of the associated NVM register
remains unchanged. Therefore, when V1/Vcc to the
device is powered down then back up, the “wiper
position” reverts to that last position written to the DCP
using a nonvolatile write operation.
Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9)
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).
Instruction Byte
While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.
The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010111. In this
case, the two Least Significant Bit’s (I1 - I0) of the
Instruction Byte are used to select the particular DCP (0
- 2). In the case of a Write to any of the DCPs (i.e. the
LSB of the Slave Address is 0), the Most Significant Bit of
the Instruction Byte (I7), determines the Write Type (WT)
performed.
If WT is “1”, then a Nonvolatile Write to the DCP
occurs.
In this case, the “wiper position” of the DCP is changed
by simultaneously writing new data to the associated
Figure 7. DCP Power-up
t
V1/Vcc
V
TRIP1
V1/Vcc (Max.)
t
purst
Maximum Wiper Recall time
0
t
trans
X9523
8
FN8209.2
August 31, 2010
WCR and NVM. Therefore, the new “wiper position” set-
ting is recalled into the WCR after V1/Vcc of the X9523
has been powered down then powered back up.
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only. The contents of
the associated NVM register remains unchanged. There-
fore, when V1/Vcc to the device is powered down then
back up, the “wiper position” reverts to that last written to
the DCP using a nonvolatile write operation.
DCP Write Operation
A write to DCPx (x = 1,2) can be performed using the
three byte command sequence shown in Figure 9.
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Reg-
ister must first be set (See “WEL: Write Enable Latch
(Volatile)” on page 10.).
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9523 after the Slave Address, if it has
been received correctly.
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9523.
Following the Instruction Byte, a Data Byte is issued to
the X9523 over SDA. The Data Byte contents is latched
into the WCR of the DCP on the first rising edge of the
clock signal, after the LSB of the Data Byte (D0) has
been issued on SDA (See Figure 29).
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. There-
fore, the Data Byte 00001111 (15
10
) corresponds to set-
ting the “wiper terminal” to tap position 15. Similarly, the
Data Byte 00011100 (28
10
) corresponds to setting the
“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1” . An example of a simple C lan-
guage function which “translates” between the tap posi-
tion (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2” .
WT
Description
0
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
1
Select a Nonvolatile Write operation to be per-
formed on the DCP pointed to by bits P1 and P0
00WT 0 0 0 P1 P0
WRITE TYPE
DCP SELECT
This bit has no effect when a Read operation is being performed.
I5I6I7 I4 I3 I2 I1 I0
Figure 8. Instruction Byte Format
S
T
A
R
T
10101110
A
C
K
WT 0 0 0 0 0 P1 P0 A
C
K
S
T
O
P
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
DATA BYTE
Figure 9. DCP Write Command Sequence
P1- P0 DCPx # Taps Max. Data Byte
0 0 RESERVED
0 1 x = 1 100 Refer to Appendix 1
1 0 x = 2 256 FFh
1 1 RESERVED
X9523
9
FN8209.2
August 31, 2010
It should be noted that all writes to any DCP of the
X9523 are random in nature. Therefore, the Data
Byte of consecutive write operations to any DCP can
differ by an arbitrary number of bits. Also, setting the
bits P1 = 1, P0 = 1 is a reserved sequence, and will
result in no ACKNOWLEDGE after sending an
Instruction Byte on SDA.
The factory default setting of all “wiper position” settings
is with 00h stored in the NVM of the DCPs. This corre-
sponds to having the “wiper teminal”
R
WX
(x = 1,2) at the
“lowest” tap position, Therefore, the resistance between
R
WX
and R
LX
is a minimum (essentially only the Wiper
Resistance,
R
W
).
DCP Read Operation
A read of DCPx (x = 1,2) can be performed using the
three byte random read command sequence shown in
Figure 10.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9523 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9523.
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W
bit set to 1. Then the X9523
issues an ACKNOWLEDGE followed by Data Byte, and
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by
bits P1 and P0.
Slave
Address
Instruction
Byte
A
C
K
A
C
K
S
t
a
r
t
S
t
o
p
Slave
Address
Data Byte
A
C
K
S
t
a
r
t
SDA Bus
Signals from
the Slave
Signals from
the Master
Figure 10. DCP Read Sequence
“Dummy” write
READ Operation
101 11100
00 000
W
T
P
1
P
0
101 11110
WRITE Operation
-
MSB
LSB
DCPx
x = 1
x = 2
“-” = DON’T CARE
S
t
a
r
t
S
t
o
p
Slave
Address
Address
Byte
Data
Byte
A
C
K
A
C
K
A
C
K
SDA Bus
Signals from
the Slave
Signals from
the Master
Figure 11. EEPROM Byte Write Sequence
Internal
Device
Address
1
01
0
0
0
0
0
WRITE Operation
X9523

X9523V20I-B

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC DUAL DCP LASER CNTRL 20TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet