25
FN8209.2
August 31, 2010
V
TRIPX
(X = 1,2,3) PROGRAMMING PARAMETERS (See Figure 28)
Notes: The above parameters are not 100% tested.
V1RO, V2RO, V3RO OUTPUT TIMING. (See Figure 25, Figure 26, Figure 27)
Notes: 1.See Figure 26 for timing diagram.
Notes: 2.See Figure 20 for equivalent load.
Notes: 3.This parameter describes the lowest possible V1/Vcc level for which the outputs V1RO, V2RO, and V3RO will be correct with respect to
their inputs (V1/Vcc, V2, V3).
Notes: 4.From MR rising edge crossing V
IH
, to V1RO rising edge crossing V
OH
.
Notes: 5.The above parameters are not 100% tested.
Parameter Description Min Typ Max Units
t
VPS
V
TRIPx
Program Enable Voltage Setup time
10 μs
t
VPH
V
TRIPx
Program Enable Voltage Hold time
10 μs
t
TSU
V
TRIPx
Setup time
10 μs
t
THD
V
TRIPx
Hold (stable) time
10 μs
t
VPO
V
TRIPx
Program Enable Voltage Off time
(Between successive adjustments)
1ms
t
wc
V
TRIPx
Write Cycle time
510 ms
V
P
Programming Voltage 10 15 V
V
ta
V
TRIPx
Program Voltage accuracy
(Programmed at 25
o
C.)
-100 +100 mV
V
tv
V
TRIP
Program variation after programming (-40 - 85
o
C).
(Programmed at 25
o
C.)
-25 +10 +25 mV
Symbol Description Condition Min. Typ. Max. Units
t
PURST
(5)
Power-on Reset delay time
POR1 = 0, POR0 = 0 25 50 75 ms
POR1 = 0, POR0 = 1 50 100 150 ms
POR1 = 1, POR0 = 0 100 200 300 ms
POR1 = 1, POR0 = 1 150 300 450 ms
t
MRD
(26)(2)(5)
MR to V1RO propagation delay
See
(1)(2)(4)
5 μs
t
MRDPW
(5)
MR pulse width 500 ns
t
RPDx
(5)
V Vcc, V2, V3 to V1RO, V2RO,
V3RO propagation
delay (respectively)
20 μs
t
Fx
(5)
V1/Vcc, V2, V3 Fall Time 20 mV/μs
t
Rx
(5)
V1/Vcc, V2, V3 Rise Time 20 mV/μs
V
RVALID
(5)
V1/Vcc for V1RO, V2RO, V3RO
Valid
(3)
.
1V
X9523
26
FN8209.2
August 31, 2010
APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Tap
Position
Data Byte
Decimal Binary
0 0 0000 0000
1 1 0000 0001
.
.
.
.
.
.
23 23 0001 0111
24 24 0001 1000
25 56 0011 1000
26 55 0011 0111
.
.
.
.
.
.
48 33 0010 0001
49 32 0010 0000
50 64 0100 0000
51 65 0100 0001
.
.
.
.
.
.
73 87 0101 0111
74 88 0101 1000
75 120 0111 1000
76 119 0111 0111
.
.
.
.
.
.
98 97 0110 0001
99 96 0110 0000
X9523
27
FN8209.2
August 31, 2010
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)
unsigned DCP1_TAP_Position(int tap_pos)
{
int block;
int i;
int offset;
int wcr_val;
offset= 0;
block = tap_pos / 25;
if (block < 0) return ((unsigned)0);
else if (block <= 3)
{ switch(block)
{ case (0): return ((unsigned)tap_pos) ;
case (1):
{
wcr_val = 56;
offset = tap_pos - 25;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
case (2):
{
wcr_val = 64;
offset = tap_pos - 50;
for (i=0; i<= offset; i++) wcr_val++ ;
return ((unsigned)--wcr_val);
}
case (3):
{
wcr_val = 120;
offset = tap_pos - 75;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
}
}
return((unsigned)01100000);
}
X9523

X9523V20I-B

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC DUAL DCP LASER CNTRL 20TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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