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X9523V20I-B

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
19
FN8209.2
August 31, 2010
TIMING DIAGRAMS
Figure 22. Bus Timing
Figure 23. WP Pin Timing
Figure 24. Write Cycle Timing
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA IN
SDA OUT
t
F
t
LOW
t
BUF
t
AA
t
R
t
HD:WP
SCL
SDA IN
WP
t
SU:WP
Clk 1 Clk 9
START
SCL
SDA
t
WC
8th bit of last byte ACK
Stop
Condition
Start
Condition
X9523
20
FN8209.2
August 31, 2010
Figure 25. Power-Up and Power-Down Timing
Figure 26. Manual Reset Timing Diagram
Figure 27. V2, V3 Timing Diagram
V1/Vcc
t
PURST
t
R
t
F
0 Volts
V
TRIP1
V1RO
t
RPD
0 Volts
t
PURST
MR
0 Volts
0 Volts
MR
V1RO
t
PURST
t
MRD
0 Volts
V1 / Vcc
V1/Vcc
V
TRIP1
t
MRPW
Vx
t
Rx
t
Fx
V
TRIPx
V
RVALID
VxRO
t
RPDx
0 Volts
Note : x = 2,3.
0 Volts
0 Volts
t
RPDx
t
RPDx
t
RPDx
V
TRIP1
V1/Vcc
X9523
21
FN8209.2
August 31, 2010
Figure 28. V
TRIPX
Programming Timing Diagram (x = 1,2,3).
Figure 29. DCP “Wiper Position” Timing
WP
t
VPS
V
P
t
VPO
SCL
SDA
t
wc
t
TSU
t
THD
V Vcc, V2, V3
V
TRIPx
00h
t
VPH
NOTE : V1/Vcc must be greater than V2, V3 when programming.
S
T
A
R
T
10101110
A
C
K
WT 0 0 0 0 0 P1 P0 A
C
K
S
T
O
P
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
DATA BYTE
SCL
SDA
Time
Rwx (x = 0,1,2)
t
wr
R
wx(n + 1)
R
wx(n - 1)
R
wx(n)
n = tap position
X9523
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

X9523V20I-B

Mfr. #:
Buy X9523V20I-B
Manufacturer:
Renesas / Intersil
Description:
IC DUAL DCP LASER CNTRL 20TSSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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