Features
Low-voltage Operation
–1.8V (V
CC
= 1.8V to 3.6V)
–2.5V (V
CC
= 2.5V to 5.5V)
Internally Organized 131,072 x 8
Two-wire Serial Interface
Schmitt Triggers, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400 kHz (1.8V) and 1 MHz (5V, 2.5V) Clock Rate
Write Protect Pin for Hardware and Software Data Protection
256-byte Page Write Mode (Partial Page Writes Allowed)
Random and Sequential Read Modes
Self-timed Write Cycle (5 ms Typical)
High Reliability
Endurance: 1,000,000 Write Cycles/Page
Data Retention: 40 Years
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP, 8-lead Ultra Thin
Small Array (SAP), and 8-ball dBGA2 Packages
Die Sales: Wafer Form, Tape and Reel and Bumped Die
Description
The AT24C1024B provides 1,048,576 bits of serial electrically erasable and program-
mable read only memory (EEPROM) organized as 131,072 words of 8 bits each. The
device’s cascadable feature allows up to four devices to share a common two-wire
bus. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP,
8-ball dBGA2 and 8-lead Ultra Thin SAP packages. In addition, the entire family is
available in 1.8V (1.8V to 3.6V) and 2.5V (2.5V to 5.5V) versions.
Two-wire Serial
EEPROM
1M (131,072 x 8)
AT24C1024B
with Two Device
Address Inputs
Rev. 5194F–SEEPR–1/08
8-lead PDIP
1
2
3
4
8
7
6
5
NC
A1
A2
GND
VCC
WP
SCL
SDA
8-lead TSSOP
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
NC
A1
A2
GND
8-lead SOIC
1
2
3
4
8
7
6
5
NC
A1
A2
GND
VCC
WP
SCL
SDA
8-lead Ultra-Thin SAP
Bottom View
VCC
WP
SCL
SDA
NC
A1
A2
GND
1
2
3
4
8
7
6
5
8-lead dBGA2
Bottom View
VCC
WP
SCL
SDA
NC
A1
A2
GND
1
2
3
4
8
7
6
5
2
5194F–SEEPR–1/08
AT24C1024B
Table 0-1. Pin Configurations
Pin Name Function
A1 Address Input
A2 Address Input
SDA Serial Data
SCL Serial Clock Input
WP Write Protect
NC No Connect
1. Absolute Maximum Ratings*
Operating Temperature..................................–55qC to +125qC
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature.....................................–65qC to +150qC
Voltage on Any Pin
with Respect to Ground....................................–1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
3
5194F–SEEPR–1/08
AT24C1024B
Figure 1-1. Block Diagram
2. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open-collector
devices.
DEVICE/ADDRESSES (A1/A2): The A1, A2 pin is a device address input that can be hardwired
or left not connected for hardware compatibility with other AT24Cxx devices. When the A1, A2
pins are hardwired, as many as four 1024K devices may be addressed on a single bus system
(device addressing is discussed in detail under the Device Addressing section). If the A1/A2 pins
are left floating, the A1/A2 pin will be internally pulled down to GND if the capacitive coupling to
the circuit board V
CC
plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting the
A1/A2 pin to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write
operations. When WP is connected high to V
CC
, all write operations to the memory are inhibited.
If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive cou-
pling to the circuit board V
CC
plane is <3 pF. If coupling is >3 pF, Atmel recommends connecting
the pin to GND. Switching WP to V
CC
prior to a write operation creates a software write-protect
function.
START
STOP
LOGIC
VCC
GND
WP
SCL
SDA
A
2
A
1
A
0
SERIAL
CONTROL
LOGIC
EN
H.V. PUMP/TIMING
EEPROM
DATA RECOVERY
SERIAL MUX
X DEC
D
OUT
/ACK
LOGIC
COMP
LOAD
INC
DATA WORD
ADDR/COUNTER
Y DEC
R/W
D
OUT
D
IN
LOAD
DEVICE
ADDRESS
COMPARATOR

AT24C1024B-TH-B

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
EEPROM 1.8V - NiPdAu 1.8V
Lifecycle:
New from this manufacturer.
Delivery:
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