M41T00SM6F Datasheet M41T00SM6F, M41T00SM6E | P13-P15

M41T00S Clock operation

Doc ID 10772 Rev 5 13/28

Table 2. TIMEKEEPER

Keys:

0 = must be set to '0'

CB = century bit

CEB = century enable bit

FT = frequency test bit

OF = oscillator fail bit

OUT = output level

S = sign bit

ST = stop bit

3.2 Calibrating the clock

The M41T00S is driven by a quartz-controlled oscillator with a nominal frequency of 32,768

Hz. The devices are tested not exceed ±35 ppm (parts per million) oscillator frequency error

at 25

C, which equates to about ±1.53 minutes per month (see Figure 10 on page 15).

When the calibration circuit is properly employed, accuracy improves to better than ±2 ppm

at 25°C.

The oscillation rate of crystals changes with temperature. The M41T00S design employs

periodic counter correction. The calibration circuit adds or subtracts counts from the

oscillator divider circuit at the divide by 256 stage, as shown in Figure 11 on page 15. The

number of times pulses which are blanked (subtracted, negative calibration) or split (added,

positive calibration) depends upon the value loaded into the five calibration bits found in the

calibration register. Adding counts speeds the clock up, subtracting counts slows the clock

down.

The calibration bits occupy the five lower order bits (D4-D0) in the calibration register 07h.

These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a

Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs

within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one

second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is

loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a

binary 6 is loaded, the first 12 will be affected, and so on.

Addr

Function/range BCD format

D7 D6 D5 D4 D3 D2 D1 D0

00h ST 10 seconds Seconds Seconds 00-59

01h OF 10 minutes Minutes Minutes 00-59

02h CEB CB 10 hours Hours (24-hour format) Century/hours 0-1/00-23

03h00000 Day of week Day 01-7

04h 0 0 10 date Date: day of month Date 01-31

05h 0 0 0 10M Month Month 01-12

06h 10 years Year Year 00-99

07h OUT FT S Calibration Calibration

Clock operation M41T00S

14/28 Doc ID 10772 Rev 5

Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator

cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of

adjustment per calibration step in the calibration register (see Figure 11 on page 15).

Assuming that the oscillator is running at exactly 32,768 Hz, each of the 31 increments in

the calibration byte would represent +10.7 or –5.35 seconds per month which corresponds

to a total range of +5.5 or –2.75 minutes per month.

Two methods are available for ascertaining how much calibration a given M41T00S may

require.

The first involves setting the clock, letting it run for a month and comparing it to a known

accurate reference and recording deviation over a fixed period of time. Calibration values,

including the number of seconds lost or gained in a given period, can be found in application

note AN934, “TIMEKEEPER

calibration.” This allows the designer to give the end user the

ability to calibrate the clock as the environment requires, even if the final product is

packaged in a non-user serviceable enclosure. The designer could provide a simple utility

that accesses the calibration byte.

The second approach is better suited to a manufacturing environment, and involves the use

of the FT/OUT pin. The pin will toggle at 512 Hz, when the Stop bit (ST, D7 of 00h) is '0,' and

the Frequency Test bit (FT, D6 of 07h) is '1.'

Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at

the test temperature. For example, a reading of 512.010124 Hz would indicate a +20 ppm

oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte

for correction. Note that setting or changing the calibration byte does not affect the

frequency test output frequency.

The FT/OUT pin is an open drain output which requires a pull-up resistor to V

for proper

operation. A 500-10k resistor is recommended in order to control the rise time. The FT bit is

cleared on power-down.

M41T00S Clock operation

Doc ID 10772 Rev 5 15/28

Figure 10. Crystal accuracy across temperature

Figure 11. Clock calibration

3.2.1 Century bit

Bits D7 and D6 of clock register 02h contain the CENTURY ENABLE bit (CEB) and the

CENTURY bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or

from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'

CB will not toggle.

3.2.2 Oscillator fail detection

If the Oscillator Fail bit (OF) is internally set to '1,' this indicates that the oscillator has either

stopped, or was stopped for some period of time and can be used to judge the validity of the

clock and date data.

AI07888

–160

0 10203040506070

Frequency (ppm)

Temperature

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

= –0.036 ppm/

± 0.006 ppm/

= K x (T – T

)

= 25

C ± 5

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

M41T00SM6F

Mfr. #:

Buy M41T00SM6F

Manufacturer:

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Real Time Clock 2.0 to 5.5V 64 (8X8)

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