M41T00SM6F Datasheet M41T00SM6F, M41T00SM6E | P7-P9

M41T00S Operation

Doc ID 10772 Rev 5 7/28

2 Operation

The M41T00S clock operates as a slave device on the serial bus. Access is obtained by

implementing a start condition followed by the correct slave address (D0h). The 8 bytes

contained in the device can then be accessed sequentially in the following order:

1. Seconds register

2. Minutes register

3. Century/hours register

4. Day register

5. Date register

6. Month register

7. Year register

8. Calibration register

The M41T00S clock continually monitors V

for an out-of-tolerance condition. Should V

fall below V

PFD

, the device terminates an access in progress and resets the device address

counter. Inputs to the device will not be recognized at this time to prevent erroneous data

from being written to the device from a an out-of-tolerance system. Once V

falls below the

switchover voltage (V

), the device automatically switches over to the battery and powers

down into an ultra-low current mode of operation to preserve battery life. If V

BAT

is less than

PFD

, the device power is switched from V

to V

BAT

when V

drops below V

BAT

. If V

BAT

greater than V

PFD

, the device power is switched from V

to V

BAT

when V

drops below

PFD

. Upon power-up, the device switches from battery to V

at V

. When V

rises

above V

PFD

, it will recognize the inputs.

For more information on battery storage life refer to application note AN1012.

2.1 2-wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a

bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must

be connected to a positive supply voltage via a pull-up resistor.

The following protocol has been defined:

● Data transfer may be initiated only when the bus is not busy.

● During data transfer, the data line must remain stable whenever the clock line is high.

● Changes in the data line, while the clock line is high, will be interpreted as control

signals.

Accordingly, the following bus conditions have been defined:

2.1.1 Bus not busy

Both data and clock lines remain high.

2.1.2 Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the

START condition.

Operation M41T00S

8/28 Doc ID 10772 Rev 5

2.1.3 Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the

STOP condition.

2.1.4 Data valid

The state of the data line represents valid data when after a start condition, the data line is

stable for the duration of the high period of the clock signal. The data on the line may be

changed during the low period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition.

The number of data bytes transferred between the start and stop conditions is not limited.

The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.

By definition a device that gives out a message is called “transmitter,” the receiving device

that gets the message is called “receiver.” The device that controls the message is called

“master.” The devices that are controlled by the master are called “slaves.”

2.1.5 Acknowledge

Each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level

put on the bus by the receiver whereas the master generates an extra acknowledge related

clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge

after the reception of each byte that has been clocked out of the slave transmitter.

The device that acknowledges has to pull down the SDA line during the acknowledge clock

pulse in such a way that the SDA line is a stable low during the high period of the

acknowledge related clock pulse. Of course, setup and hold times must be taken into

account. A master receiver must signal an end of data to the slave transmitter by not

generating an acknowledge on the last byte that has been clocked out of the slave. In this

case the transmitter must leave the data line high to enable the master to generate the

STOP condition.

Figure 4. Serial bus data transfer sequence

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION

CHANGE OF

DATA ALLOWED

STOP

CONDITION

M41T00S Operation

Doc ID 10772 Rev 5 9/28

Figure 5. Acknowledgement sequence

2.2 READ mode

In this mode the master reads the M41T00S slave after setting the slave address (see

Figure 7 on page 10). Following the WRITE mode control bit (R/W

=0) and the acknowledge

bit, the word address 'An' is written to the on-chip address pointer. Next the START condition

and slave address are repeated followed by the READ mode control bit (R/W

=1). At this

point the master transmitter becomes the master receiver. The data byte which was

addressed will be transmitted and the master receiver will send an acknowledge bit to the

slave transmitter. The address pointer is only incremented on reception of an acknowledge

clock. The M41T00S slave transmitter will now place the data byte at address An+1 on the

bus, the master receiver reads and acknowledges the new byte and the address pointer is

incremented to “An+2.”

This cycle of reading consecutive addresses will continue until the master receiver sends a

STOP condition to the slave transmitter.

The system-to-user transfer of clock data will be halted whenever the address being read is

a clock address (00h to 06h). The update will resume due to a stop condition or when the

pointer increments to any non-clock address (07h).

Note: This is true both in READ mode and WRITE mode.

An alternate READ mode may also be implemented whereby the master reads the

M41T00S slave without first writing to the (volatile) address pointer. The first address that is

read is the last one stored in the pointer (see Figure 8 on page 10).

Figure 6. Slave address location

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

START

CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

M41T00SM6F

Mfr. #:

Buy M41T00SM6F

Manufacturer:

STMicroelectronics

Description:

Real Time Clock 2.0 to 5.5V 64 (8X8)

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M41T00SM6F

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