AMIS−30511
http://onsemi.com
18
Warning, Error Detection and Diagnostics Feedback
Thermal Warning and Shutdown
When junction temperature rises above TTW, the thermal
warning bit <TW> is set (Table 25: SPI Status Register 0).
If junction temperature increases above thermal shutdown
level, then the circuit goes in “thermal shutdown” mode
(<TSD>) and all driver transistors are disabled (high
impedance) (Table 27: SPI Status Register 2). The
conditions to reset flag <TSD> is to be at a temperature
lower than TTW and to clear the <TSD> flag by reading it
using any SPI read command.
Over−Current Detection
The over−current detection circuit monitors the load
current in each activated output stage. If the load current
exceeds the over−current detection threshold, then the
over−current flag is set and the drivers are switched off to
reduce the power dissipation and to protect the integrated
circuit. Each driver transistor has an individual detection bit
in the Table 26: SPI Status Register 1 and Table 27: SPI
Status Register 2 (<OVCXij> and <OVCYij>). Error
condition is latched and the microcontroller needs to clean
the status bits to reactivate the drivers.
NOTE: Successive reading the SPI Status Registers 1 and 2 in
case of a short circuit condition, may lead to damage to
the drivers.
Open Coil Detection
Open coil detection is based on the observation of 100
percent duty cycle of the PWM regulator. If in a coil 100
percent duty cycle is detected for longer than 200ms then the
related driver transistors are disabled (high−impedance) and
an appropriate bit in the SPI status register is set (<OPENX>
or <OPENY>). (Table 25: SPI Status Register 0).
Charge Pump Failure
The charge pump is an important circuit that guarantees
low Rdson for all drivers, especially for low supply voltages.
If supply voltage is too low or external components are not
properly connected to guarantee Rdson of the drivers, then
the bit <CPFAIL> is set in the Table 25: SPI Status Register
0. Also after power−on−reset the charge pump voltage will
need some time to exceed the required threshold. During that
time <CPFAIL> will be set to “1”.
Error Output
This is a digital output to flag a problem to the external
microcontroller. The signal on this output is active low and
the logic combination of:
NOT(ERRB) = <TW> OR <TSD> OR <OVCXij> OR <
OVCYij> OR <OPENi> OR <CPFAIL>
CLR pin (=Hard Reset)
Logic 0 on CLR pin allows normal operation of the chip.
To reset the complete digital inside AMIS−30511, the input
CLR needs to be pulled to logic 1 during minimum time
given by T
CLR
. (Table 5: AC Parameters) This reset function
clears all internal registers without the need of a
power−cycle. The operation of all analog circuits is
depending on the reset state of the digital, charge pump
remains active. Logic 0 on CLR pin resumes normal
operation again.
Sleep Mode
The bit <SLP> in Table 13: SPI Control Register 2 is
provided to enter a so−called “sleep mode”. This mode
allows reduction of current−consumption when the motor is
not in operation. The effect of sleep mode is as follows:
• The drivers are put in HiZ
• All analog circuits are disabled and in low−power mode
• All internal registers are maintaining their logic content
• NXT and DIR inputs are forbidden
• SPI communication remains possible (slight current
increase during SPI communication)
• Reset of chip is possible through CLR pin
• Oscillator and digital clocks are silent, except during
SPI communication
Normal operation is resumed after writing logic ‘0’ to bit
<SLP>. A start−up time is needed for the charge pump to
stabilize. After this time, NXT commands can be issued.
