LTC2482
20
2482fc
APPLICATIONS INFORMATION
PRESERVING THE CONVERTER ACCURACY
The LTC2482 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling, PCB
layout, antialiasing circuits, line frequency perturbations
and so on. Nevertheless, in order to preserve the extreme
accuracy capability of this part, some simple precautions
are required.
Digital Signal Levels
The LTC2482’s digital interface is easy to use. Its digital
inputs (f
O
, CS and SCK in external SCK mode of opera-
tion) accept standard CMOS logic levels and the internal
hysteresis receivers can tolerate edge transition times as
slow as 100μs. However, some considerations are required
to take advantage of the exceptional accuracy and low
supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(V
CC
– 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (f
O
, CS and SCK
in external SCK mode of operation) is within this range,
the power supply current may increase even if the signal
in question is at a valid logic level.
For micropower operation, it is recommended to drive all
digital input signals to full CMOS levels [V
IL
< 0.4V and
V
OH
> (V
CC
– 0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins can
severely disturb the analog to digital conversion process.
Undershoot and overshoot occur because of the imped-
ance mismatch of the circuit board trace at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver
to the LTC2482. For reference, on a regular FR-4 board,
signal propagation velocity is approximately 183ps/inch
for internal traces and 170ps/inch for surface traces.
Thus, a driver generating a control signal with a minimum
transition time of 1ns must be connected to the converter
pin through a trace shorter than 2.5 inches. This problem
becomes particularly diffi cult when shared control lines are
used and multiple refl ections may occur. The solution is
to carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2482 pin will eliminate this
problem but will increase the driver power dissipation. A
series resistor between 27Ω and 56Ω placed near the driver
output pin will also eliminate this problem without additional
power dissipation. The actual resistor value depends upon
the trace impedance and connection topology.
SDO
SCK
(INTERNAL)
CS
LSBMSBSIG
BIT 4 BIT 0BIT 19 BIT 18 BIT 17 BIT 16BIT 20BIT 21BIT 22
EOC
BIT 23
DATA OUTPUT CONVERSIONCONVERSION
2482 F09
V
CC
f
O
V
REF
IN
+
IN
–
SCK
SDO
CS
GND
210
INT/EXT CLOCK
3
4
5
9
7
8,1
6
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG
INPUT
1μF
2.7V TO 5.5V
LTC2482
2-WIRE
SPI INTERFACE
10k
V
CC
Figure 9. Internal Serial Clock, CS = 0 Continuous Operation
