LTC2482
25
2482fc
APPLICATIONS INFORMATION
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode volt-
age difference (V
REFCM
– V
INCM
) and a 5V reference, each
Ohm of reference source resistance introduces an extra
(V
REFCM
– V
INCM
)/(V
REF
• R
EQ
) full-scale gain error which
is 0.067ppm when using the internal oscillator (50Hz/60Hz
rejection). If an external clock is used, the corresponding
extra gain error is 0.22 • 10
–6
• f
EOSC
ppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specifi cation can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by V
REF
+
and GND, the expected drift of the dynamic current gain
error will be insignifi cant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be suffi cient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(±10nA max), results in a small gain error. A 100Ω source
resistance will create a 0.05μV typical and 0.5μV maximum
full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2482 produces
6.8ps with a notch frequency of 55Hz, for simultaneous
50Hz/60Hz rejection. The actual output data rate will de-
pend upon the length of the sleep and data output phases
which are controlled by the user and which can be made
insignifi cantly short. When operated with an external
conversion clock (f
O
connected to an external oscillator),
the LTC2482 output data rate can be increased as desired.
The duration of the conversion phase is 41036/f
EOSC
.
An increase in f
EOSC
over the nominal 307.2kHz will
translate into a proportional increase in the maximum
output data rate. The increase in output rate is neverthe-
less accompanied by three potential effects, which must
be carefully considered.
First, a change in f
EOSC
will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line fre-
quency. In many applications, the subsequent performance
degradation can be substantially reduced by relying upon
the LTC2482’s exceptional common mode rejection and by
carefully eliminating common mode to differential mode
conversion sources in the input circuit. The user should
avoid single-ended input fi lters and should maintain a
very high degree of matching and symmetry in the circuits
driving the IN
+
and IN
pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (C
IN
, C
REF
) are used, the
previous section provides formulae for evaluating the effect
of the source resistance upon the converter performance for
any value of f
EOSC
. If small external input and/or reference
capacitors (C
IN
, C
REF
) are used, the effect of the external
source resistance upon the LTC2482 typical performance
can be inferred from Figures 12, 13, 14 and 15 in which
the horizontal axis is scaled by 307200/f
EOSC
.
Third, an increase in the frequency of the external oscillator
above 1MHz (a more than 3× increase in the output data
rate) will start to decrease the effectiveness of the internal
autocalibration circuits. This will result in a progressive
V
IN
/V
REF
(V)
–0.5
INL (ppm OF V
REF
)
2
6
10
0.3
2482 F18
–2
–6
0
4
8
–4
–8
–10
–0.3
–0.1
0.1
0.5
V
CC
= 5V
V
REF
= 5V
V
IN(CM)
= 2.5V
T
A
= 25°C
C
REF
= 10μF
R = 1k
R = 500Ω
R = 100Ω
Figure 18. INL vs Differential Input Voltage and
Reference Source Resistance for C
REF
> 1μF
LTC2482
26
2482fc
APPLICATIONS INFORMATION
OUTPUT DATA RATE (READINGS/SEC)
–10
OFFSET ERROR (ppm OF V
REF
)
10
30
50
0
20
40
20 40 60 80
2482 F19
10010030507090
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
V
IN
= 0V
f
O
= EXT CLOCK
T
A
= 85°C
T
A
= 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
0
+FS ERROR (ppm OF V
REF
)
500
1500
2000
2500
3500
10
50
70
2482 F20
1000
3000
40
90
100
20
30
60 80
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
f
O
= EXT CLOCK
T
A
= 85°C
T
A
= 25°C
Figure 19. Offset Error vs Output Data Rate and Temperature Figure 20. +FS Error vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
–3500
–FS ERROR (ppm OF V
REF
)
–3000
–2000
–1500
–1000
0
10
50
70
2482 F21
–2500
–500
40
90
100
20
30
60 80
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
f
O
= EXT CLOCK
T
A
= 85°C
T
A
= 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION (BITS)
12
16
18
22
10
50
70
2482 F22
14
20
40
90
100
20
30
60 80
T
A
= 25°C
T
A
= 85°C
V
IN(CM)
= V
REF(CM)
V
CC
= V
REF
= 5V
f
O
= EXT CLOCK
RES = LOG 2 (V
REF
/INL
MAX
)
Figure 21. –FS Error vs Output Data Rate and Temperature Figure 22. Resolution (INL
MAX
≤ 1LSB)
vs Output Data Rate and Temperature
OUTPUT DATA RATE (READINGS/SEC)
0
–10
OFFSET ERROR (ppm OF V
REF
)
–5
5
10
20
10
50
70
2482 F23
0
15
40
90
100
20
30
60 80
V
CC
= 5V, V
REF
= 2.5V
V
CC
= V
REF
= 5V
V
IN(CM)
= V
REF(CM)
V
IN
= 0V
f
O
= EXT CLOCK
T
A
= 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
10
RESOLUTION (BITS)
12
16
18
22
10
50
70
2482 F24
14
20
40
90
100
20
30
60 80
V
CC
= 5V, V
REF
= 2.5V
V
CC
= V
REF
= 5V
V
IN(CM)
= V
REF(CM)
V
IN
= 0V
REF
= GND
f
O
= EXT CLOCK
T
A
= 25°C
RES = LOG 2 (V
REF
/INL
MAX
)
Figure 23. Offset Error vs Output
Data Rate and Reference Voltage
Figure 24. Resolution (INL
MAX
) ≤ 2LSB vs
Output Data Rate and Reference Voltage
LTC2482
27
2482fc
APPLICATIONS INFORMATION
degradation in the converter accuracy and linearity. Typical
measured performance curves for output data rates up to
100 readings per second are shown in Figures 19 to 24. In
order to obtain the highest possible level of accuracy from
this converter at output data rates above 20 readings per
second, the user is advised to maximize the power supply
voltage used and to limit the maximum ambient operating
temperature. In certain circumstances, a reduction of the
differential reference voltage may be benefi cial.
Input Bandwidth
The combined effect of the internal SINC
4
digital fi lter and
of the analog and digital autocalibration circuits deter-
mines the LTC2482 input bandwidth. When the internal
oscillator is used the 3dB input bandwidth is 3.3Hz. If an
external conversion clock generator of frequency f
EOSC
is connected to the f
O
pin, the 3dB input bandwidth is
10.7 • 10
–6
• f
EOSC
.
Due to the complex fi ltering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a fi rst order fi lter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2482 input bandwidth is shown in
Figure 25. When an external oscillator of frequency f
EOSC
is used, the shape of the LTC2482 input bandwidth can
be derived from Figure 25 in which the horizontal axis is
scaled by f
EOSC
/307200.
The conversion noise (600nV
RMS
typical for V
REF
= 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is 47nV√Hz
for an infi nite bandwidth source and 64nV√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
amplifi cation circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is
a high gain, low bandwidth amplifi er stage followed by a
high bandwidth unity-gain buffer.
When external amplifi ers are driving the LTC2482, the
ADC input referred system noise calculation can be
simplifi ed by Figure 26. The noise of an amplifi er driving
the LTC2482 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass fi lter with a
corner frequency f
i
. The amplifi er noise spectral density
is n
i
. From Figure 26, using f
i
as the x-axis selector, we
can fi nd on the y-axis the noise equivalent bandwidth freq
i
of the input driving amplifi er. This bandwidth includes
the band limiting effects of the ADC internal calibration
and fi ltering. The noise of the driving amplifi er referred
to the converter input and including all these effects can
be calculated as N = n
i
• √freq
i
. The total system noise
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
INPUT SIGNAL ATTENUATION (dB)
–3
–2
–1
0
4
2482 F25
–4
–5
–6
1
2
3
5
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
1
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
10
0.1 1 10 100 1k 10k 100k 1M
2482 F26
0.1
100
Figure 25. Input Signal Bandwidth Using the Internal Oscillator Figure 26. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source

LTC2482CDD#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit Delta Sigma ADC
Lifecycle:
New from this manufacturer.
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