LTC2482
8
2482fc
PIN FUNCTIONS
GND (Pin 1): Ground. This pin should be tied to ground;
however, in order to remain pin compatible with the
LTC2480/LTC2484, this pin may be driven high or low.
V
CC
(Pin 2): Positive Supply Voltage. Bypass to GND (Pin 8)
with a 1μF tantalum capacitor in parallel with 0.1μF ceramic
capacitor as close to the part as possible.
V
REF
(Pin 3): Positive Reference Input. The voltage on
this pin can have any value between 0.1V and V
CC
. The
negative reference input is GND (Pin 8).
IN
+
(Pin 4), IN
–
(Pin 5): Differential Analog Inputs. The
voltage on these pins can have any value between GND
– 0.3V and V
CC
+ 0.3V. Within these limits the converter
bipolar input range (V
IN
= IN
+
– IN
–
) extends from –0.5 •
V
REF
to 0.5 • V
REF
. Outside this input range the converter
produces unique overrange and underrange output codes.
CS (Pin 6): Active Low Chip Select. A low on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion the ADC automatically enters
the sleep mode and remains in this low power state as
long as CS is high. A low-to-high transition on CS during
the data output transfer aborts the data transfer and starts
a new conversion.
SDO (Pin 7): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select, CS, is high (CS = V
CC
), the SDO pin
is in a high impedance state. During the conversion and
sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS low.
GND (Pin 8): Ground. Shared pin for analog ground, digital
ground and reference ground. Should be connected directly
to a ground plane through a minimum impedance.
SCK (Pin 9): Bidirectional Digital Clock Pin. In internal serial
clock operation mode, SCK is used as the digital output for
the internal serial interface clock during the data output
period. In external serial clock operation mode, SCK is used
as the digital input for the external serial interface clock
during the data output period. A weak internal pull-up is
automatically activated in internal serial clock operation
mode. The serial clock operation mode is determined by
the logic level applied to the SCK pin at power up or during
the most recent falling edge of CS.
f
O
(Pin 10): Frequency Control Pin. Digital input that
controls the conversion clock. When f
O
is connected to
GND the converter uses its internal oscillator running at
307.2kHz. The conversion clock may also be overridden by
driving the f
O
pin with an external clock in order to change
the output rate or the digital fi lter rejection null.
Exposed Pad (Pin 11): This pin is ground and should be
soldered to the PCB, GND plane. For prototyping purposes
this pin may remain fl oating.
