1999 Nov 23 2
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74ALVCH16652
FEATURES
• In accordance with JEDEC standard no. 8-1A
• CMOS low power consumption
• MULTIBYTE flow-through pin-out architecture
• Low inductance, multiple supply and ground pins for
minimum noise and ground bounce
• Direct interface with TTL levels
• All data inputs have bus hold
• Output drive capability 50 Ω transmission lines at 85 °C
• Current drive ±24 mA at 3.0 V.
DESCRIPTION
The 74ALVCH16652 consists of 16 non-inverting bus
transceiver circuits with 3-state outputs, D-type flip-flops
and control circuitry arranged for multiplexed transmission
of data directly from the data bus or from the internal
storage registers.
Data on the ‘A’ or ‘B’, or both buses, will be stored in the
internal registers, at the appropriate clock inputs
(nCP
AB
or nCP
BA
) regardless of the select inputs (nS
AB
and nS
BA
) or output enable (nOE
AB
and nOE
BA
) control
inputs.
Depending on the select inputs nS
AB
and nS
BA
data can
directly go from input to output (real-time mode) or data
can be controlled by the clock (storage mode), when OE
inputs permit this operating mode.
The output enable inputs nOE
AB
and nOE
BA
determine the
operation mode of the transceiver. When nOE
AB
is LOW,
no data transmission from nB
n
to nA
n
is possible and when
nOE
BA
is HIGH, no data transmission from nB
n
to nA
n
is
possible.
When nS
AB
and nS
BA
are in the real-time transfer mode, it
is also possible to store data without using the internal
D-type flip-flops by simultaneously enabling nOE
AB
and
nOE
BA
. In this configuration each output reinforces its
input.
Active bus hold circuitry is provided to hold unused or
floating data inputs at a valid logic level.
QUICK REFERENCE DATA
Ground = 0; T
amb
=25°C; t
r
=t
f
= 2.5 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
+ Σ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
C
L
= output load capacitance in pF;
f
o
= output frequency in MHz;
V
CC
= supply voltage in Volts;
Σ (C
L
× V
CC
2
× f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PHL
/t
PLH
propagation delay nA
n
,nB
n
to nB
n
,nA
n
C
L
= 50 pF; V
CC
= 3.3 V 2.6 ns
f
max
maximum clock frequency 350 MHz
C
I
input capacitance 4.0 pF
C
PD
power dissipation capacitance per latch notes 1 and 2
outputs enabled 22 pF
outputs disabled 4.0 pF
