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74ALVCH16652DGGS

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
1999 Nov 23 12
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74ALVCH16652
AC WAVEFORMS
Fig.6 The inputs nA
n
, nB
n
to outputs nB
n
, nA
n
propagation delay times.
handbook, halfpage
MNA320
nA
n
, nB
n
input
nB
n
, nA
n
output
t
PHL
t
PLH
GND
V
I
V
M
V
M
V
OH
V
OL
Fig.7 The inputs nS
AB
, nS
BA
to outputs nB
n
, nA
n
propagation delays.
handbook, halfpage
MNA321
nS
AB
, nS
BA
input
nB
n
, nA
n
output
t
PHL
t
PLH
GND
V
I
V
M
V
M
V
OH
V
OL
Fig.8 The nA
n
, nB
n
to nCP
AB
, nCP
BA
set-up and hold times, clock nCP
AB
, nCP
BA
pulse width, maximum clock
pulse frequency and the nCP
AB
, nCP
BA
to output nB
n
, nA
n
propagation delay times.
handbook, full pagewidth
MNA322
t
h
t
su
t
W
1/f
max
t
h
t
su
t
PHL
t
PLH
nCP
AB
, nCP
BA
output
nA
n
, nB
n
input
GND
V
I
V
OH
V
OL
nB
n
, nA
n
output
V
OH
V
OL
V
M
V
M
1999 Nov 23 13
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74ALVCH16652
Fig.9 The OE inputs (nOE
AB
, nOE
BA
) to outputs nA
n
, nB
n
enable and disable times and the input rise and fall
times.
handbook, full pagewidth
MNA323
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
V
Y
V
X
outputs
enabled
output
LOW-to-OFF
OFF-to-LOW
output
HIGH-to-OFF
OFF-to-HIGH
nOE
BA
input
V
I
V
OL
V
OH
V
CC
V
M
V
M
GND
nOE
AB
input
V
I
GND
GND
t
PZL
t
PZH
V
M
V
M
Notes: V
CC
= 2.3 to 2.7 V
V
M
= 0.5V
CC
;
V
X
=V
OL
+ 150 mV;
V
Y
=V
OH
− 150 mV;
V
I
=V
CC
;
V
OL
and V
OH
are typical output voltage drop that occur with the output load.
Notes: V
CC
= 3.0 to 3.6 V and V
CC
= 2.7 V
V
M
= 1.5 V;
V
X
=V
OL
+ 300 mV;
V
Y
=V
OH
− 300 mV;
V
I
= 2.7 V;
V
OL
and V
OH
are typical output voltage drop that occur with the output load.
1999 Nov 23 14
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74ALVCH16652
Fig.10 Load circuitry for switching times.
V
CC
V
I
<2.7 V V
CC
2.7 to 3.6 V 2.7 V
TEST S1
t
PLH
/t
PHL
open
t
PLZ
/t
PZL
2 × V
CC
t
PHZ
/t
PZH
GND
handbook, full pagewidth
open
GND
50 pF
2 × V
CC
V
CC
V
I
V
O
MNA296
D.U.T.
C
L
R
T
R
L
500 Ω
R
L
500 Ω
PULSE
GENERATOR
S1
Definitions for test circuit.
C
L
= load capacitance including jig and probe capacitance
(See Chapter “AC characteristics”).
R
L
= load resistance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
APPLICATION INFORMATION
Fig.11 Real-time transfer; bus B to bus A.
handbook, halfpage
MNA325
BUS A
BUS B
LL
CP
AB
X
CP
BA
X
S
AB
X
S
BA
L
OE
AB
OE
BA
Fig.12 Real-time transfer; bus A to bus B.
handbook, halfpage
MNA326
BUS A
BUS B
HH
CP
AB
X
CP
BA
X
S
AB
L
S
BA
X
OE
AB
OE
BA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

74ALVCH16652DGGS

Mfr. #:
Buy 74ALVCH16652DGGS
Manufacturer:
Nexperia
Description:
Bus Transceivers 16-Bit Transceiver/ Register Duel Enable
Lifecycle:
New from this manufacturer.
Delivery:
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