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74ALVCH16652DGGS

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
1999 Nov 23 9
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74ALVCH16652
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground=0V).
Notes
1. All typical values are measured at T
amb
=25°C.
2. Valid for data inputs of bus hold parts.
SYMBOL PARAMETER
TEST CONDITIONS T
amb
= −40 TO +85 °C
UNIT
V
I
(V) OTHER V
CC
(V) MIN. TYP.
(1)
MAX.
V
IH
HIGH-level input voltage 2.3 to 2.7 1.7 1.2 − V
2.7 to 3.6 2.0 1.5 −
V
IL
LOW-level input voltage 2.3 to 2.7 − 1.2 0.7 V
2.7 to 3.6 − 1.5 0.8
V
OH
HIGH-level output voltage V
IH
or V
IL
I
O
= −100 µA 2.3 to 3.6 V
CC
− 0.2 V
CC
− V
I
O
= −6 mA 2.3 V
CC
− 0.3 V
CC
− 0.08 −
I
O
= −12 mA 2.3 V
CC
− 0.6 V
CC
− 0.26 −
I
O
= −12 mA 2.7 V
CC
− 0.5 V
CC
− 0.14 −
I
O
= −12 mA 3.0 V
CC
− 0.6 V
CC
− 0.09 −
I
O
= −24 mA 3.0 V
CC
− 1.0 V
CC
− 0.28 −
V
OL
LOW-level output voltage V
IH
or V
IL
I
O
= 100 µA 2.3 to 3.6 − GND 0.20 V
I
O
=6mA 2.3 − 0.07 0.40
I
O
=12mA 2.3 − 0.15 0.70
I
O
=12mA 2.7 − 0.14 0.40
I
O
=24mA 3.0 − 0.27 0.55
I
l
input leakage current V
CC
or
GND
2.3 to 3.6 − 0.1 5 µA
I
OZ
3-state output OFF-state
current
V
IH
or V
IL
V
O
=V
CC
or
GND
2.3 to 3.6 − 0.1 10 µA
I
CC
quiescent supply voltage V
CC
or
GND
I
O
= 0 2.3 to 3.6 − 0.2 40 µA
∆I
CC
additional quiescent supply
current given per data I/O
pin with bus hold
V
CC
− 0.6 I
O
= 0 2.3 to 3.6 − 150 750 µA
I
BHL
bus hold LOW sustaining
current
0.7
(2)
2.3
(2)
45 −−µA
0.8
(2)
3.0
(2)
75 150 −
I
BHH
bus hold HIGH sustaining
current
1.7
(2)
2.3
(2)
−45 −−µA
2.0
(2)
3.0
(2)
−75 −175 −
I
BHLO
bus hold LOW overdrive
current
3.6
(2)
500 −−µA
I
BHHO
bus hold LOW overdrive
current
3.6
(2)
−500 −−µA
1999 Nov 23 10
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74ALVCH16652
AC CHARACTERISTICS FOR V
CC
= 2.3 TO 2.7 V
Ground = 0 V; t
r
=t
f
≤2.0 ns; C
L
=30pF.
Note
1. All typical values are measured at T
amb
=25°C and V
CC
= 2.5 V.
SYMBOL PARAMETER
TEST CONDITIONS T
amb
= −40 TO +85 °C
UNIT
WAVEFORMS V
CC
(V) MIN. TYP.
(1)
MAX.
t
PHL
/t
PLH
propagation delay
nA
n
,nB
n
to nB
n
,nA
n
see Figs 6 and 10 2.3 to 2.7 1.0 2.7 4.8 ns
propagation delay
nCP
AB
, nCP
BA
to nB
n
,nA
n
see Figs 8 and 10 2.3 to 2.7 1.0 3.4 6.8 ns
propagation delay
nS
AB
,nS
BA
to nB
n
, nA
n
see Figs 7 and 10 2.3 to 2.7 1.0 3.4 5.6 ns
t
PZH
/t
PZL
3-state output enable time
nOE
AB
to nB
n
see Figs 9 and 10 2.3 to 2.7 1.0 2.6 4.5 ns
t
PHZ
/t
PLZ
3-state output disable time
nOE
AB
to nB
n
see Figs 9 and 10 2.3 to 2.7 1.6 2.7 4.5 ns
t
PZH
/t
PZL
3-state output enable time
nOE
BA
to nA
n
see Figs 9 and 10 2.3 to 2.7 3.3 2.8 4.5 ns
t
PHZ
/t
PLZ
3-state output disable time
nOE
BA
to nA
n
see Figs 9 and 10 2.3 to 2.7 3.3 2.5 4.5 ns
t
W
clock pulse width HIGH or
LOW nCP
AB
or nCP
BA
see Figs 8 and 10 2.3 to 2.7 2.2 1.2 − ns
t
su
set-up time
nA
n
,nB
n
to nCP
AB
, nCP
BA
see Figs 8 and 10 2.3 to 2.7 2.2 0.2 − ns
t
h
hold time
nA
n
,nB
n
to nCP
AB
, nCP
BA
see Figs 8 and 10 2.3 to 2.7 0.6 0.1 − ns
f
max
maximum clock pulse
frequency
see Figs 8 and 10 2.3 to 2.7 150 300 − MHz
1999 Nov 23 11
Philips Semiconductors Product specification
16-bit transceiver/register with dual enable; 3-state 74ALVCH16652
AC CHARACTERISTICS FOR V
CC
= 2.7 V AND V
CC
= 3.0 TO 3.6 V
Ground = 0 V; t
r
=t
f
≤2.5 ns; C
L
=50pF.
Notes
1. All typical values are measured at T
amb
=25°C.
2. Typical values at V
CC
= 3.3 V.
SYMBOL PARAMETER
TEST CONDITIONS T
amb
= −40 TO +85 °C
UNIT
WAVEFORMS V
CC
(V) MIN. TYP.
(1)
MAX.
t
PHL
/t
PLH
propagation delay
nA
n
,nB
n
to nB
n
,nA
n
see Figs 6 and 10 2.7 − 2.8 4.5 ns
3.0 to 3.6 1.0 2.6
(2)
3.9
propagation delay
nCP
AB
, nCP
BA
to nB
n
,nA
n
see Figs 8 and 10 2.7 − 3.1 5.2 ns
3.0 to 3.6 1.4 2.9
(2)
4.5
propagation delay
nS
AB
,nS
BA
to nB
n
,nA
n
see Figs 7 and 10 2.7 − 3.5 6.4 ns
3.0 to 3.6 1.3 3.1
(2)
5.3
t
PZH
/t
PZL
3-state output enable time
nOE
AB
to nB
n
see Figs 9 and 10 2.7 − 2.4 4.6 ns
3.0 to 3.6 1.0 2.2
(2)
4.0
t
PHZ
/t
PLZ
3-state output disable time
nOE
AB
to nB
n
see Figs 9 and 10 2.7 − 3.4 5.1 ns
3.0 to 3.6 1.4 2.7
(2)
4.5
t
PZH
/t
PZL
3-state output enable time
nOE
BA
to nA
n
see Figs 9 and 10 2.7 − 3.0 4.6 ns
3.0 to 3.6 1.0 2.2
(2)
4.0
t
PHZ
/t
PLZ
3-state output disable time
nOE
BA
to nA
n
see Figs 9 and 10 2.7 − 3.1 5.1 ns
3.0 to 3.6 1.1 2.9
(2)
4.5
t
W
clock pulse width HIGH or
LOW nCP
AB
or nCP
BA
see Figs 8 and 10 2.7 3.3 1.0 − ns
3.0 to 3.6 3.3 0.7
(2)
−
t
su
set-up time
nA
n
,nB
n
to nCP
AB
, nCP
BA
see Figs 8 and 10 2.7 1.7 0.2 − ns
3.0 to 3.6 1.4 0.3
(2)
−
t
h
hold time
nA
n
,nB
n
to nCP
AB
, nCP
BA
see Figs 8 and 10 2.7 0.4 0.1 − ns
3.0 to 3.6 0.7 0.2
(2)
−
f
max
maximum clock pulse
frequency
see Figs 8 and 10 2.7 150 320 − MHz
3.0 to 3.6 150 320
(2)
−
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

74ALVCH16652DGGS

Mfr. #:
Buy 74ALVCH16652DGGS
Manufacturer:
Nexperia
Description:
Bus Transceivers 16-Bit Transceiver/ Register Duel Enable
Lifecycle:
New from this manufacturer.
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