NCP1339
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25
Valley 1
3.21.61.51.41.11.00.90.8 1.2
V
FB
(V)
Fault !
Operating Mode
Valley 3
Valley 4
Valley 5
Valley 6
FF
Valley 2
2.01.81.7
V
FB
decreases
V
FB
increases
Figure 53. Valley Lockout Thresholds Without IFF Pin
FB (V)
Operating Mode
Valley 1
Valley 2
Valley 3
Valley 4
Valley 5
Valley 6
FF
V
IFF
V
IFF
+A
V
IFF
+2A
V
IFF
+3A
V
IFF
+4A
V
IFF
+6A
(1.4 V)
B+A
B+2A B+3A B+4A B+6A
(2.0 V)
1.4
6
600
IFF
IFF
VV
A
BV mV
=
=
200 mV
Figure 54. Valley Lockout Thresholds With IFF Pin
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26
Over Power Compensation (OPP)
The power delivered by a QR flyback stage is an
increasing function of the bulk voltage, V
bulk
. It is however
desirable to clamp the power delivery to limit the stress on
the power components that can otherwise be excessive
during transient or fault conditions.
An integrated overpower circuit provides a relatively
constant output power across bulk voltage, V
bulk
.
Practically, the maximum peak current is made a decreasing
function of the bulk voltage. The direct measure of the V
bulk
high−voltage rail would cause losses in the sensing network
and hence alter the standby efficiency.
Instead, the auxiliary winding voltage (V
AUX
) is used.
During power−switch on−time, V
AUX
provides a negative
voltage that is a V
bulk
portion (input voltage scaled down by
the primary to auxiliary winding turns ratio) as shown in
Figure 55. The negative voltage applied to the pin is referred
as V
OPP
. The maximum internal current setpoint (V
CS(OPP)
)
is the sum of V
OPP
and peak current sense threshold, V
ILIM1
.
The current setpoint is calculated using Equation 7.
V
CS(OPP)
+ V
ILIM1
) V
OPP
(eq. 7)
That is that:
V
CS(OPP)
+ V
ILIM1
*
ǒ
N
AUX
N
P
@ V
BULK
Ǔ
(eq. 8)
AUX
BULK
P
N
V
N
Figure 55. Auxiliary Winding Voltage Waveform
V
AUX
(V)
For example, (V
OPP
= −0.25 V) results in a current
setpoint of 0.55 V. In general, V
OPP
is selected in the range
of −200 mV at the highest line level. Refer to application
notes for more details.
ǒ
V
CS(OPP)
+ 0.8−0.25 + 0.55 + 68.75% @ 0.8 + 68.75% @ V
ILIM1
Ǔ
The OPP pin is not designed to operate below –250 mV
which corresponds to a 31.25% decrease of the maximum
current limit. If a lower voltage happens to be applied, the
internal ESD diode that clamps OPP pin negative voltages
may turn on and lead to carriers injection within the die. To
avoid possible resulting disturbance, care must be taken to
limit the current sourced by the diode below 2 mA. If the
circuitry of Figure 56 is used, a conservative condition is:
V
AUX,max
R
OPP1
w −2 mA å R
OPP1
w*
V
AUX,max
2m
(eq. 9)
Finally, please note that another comparator internally
fixes the maximum peak current set point to V
ILIM1
. Hence,
even if the OPP pin is adversely biased above 0 V, the current
setpoint remains clamped to 0.8 V typically.
For optimum performance over temperature, we
recommend keeping the low−side OPP resistor below 3 kW.
Current Setpoint
As explained in this operating description, the current
setpoint is affected by several functions. Figure 56
summarizes these interactions. As shown by this figure, the
current setpoint is FB/4. However, this value is limited by
the following functions:
This level is clamped during the soft−start phase. The
setpoint is actually limited by a clamp level ramping
from 0 to 0.8 V within 4 ms.
It is also limited by the OPP function: during the
on−time, a negative voltage is applied to the OPP pin.
This voltage is summed with a 0.8−V voltage reference
to form the actual maximum setpoint (see OPP section).
NCP1339
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27
It must be noted that the OPP pin voltage is high during
the off−time. The summer is designed to face this
situation without degradation of the circuitry.
A minimum setpoint is forced that equals to V
freeze
(0.2 V, typically).
In addition, a second OCP comparator ensures that in
any case the current setpoint is limited to 0.8 V. This
prevents the over−current limit from being increased
due to the OPP function if a positive voltage is
accidentally applied during the on−time. Hence, even in
this faulty condition, the MOSFET current setpoint
remains limited to V
ILIM1
(0.8 V typically).
Figure 56. Current Setpoint
FB
CS
Rcs
Rs
+
PWM latch
RESET
275−ns
LEB
DRV
OPP
+
OCP COMP
+
0.8 V
3R
R
0.8V
+
+
Frozen
current
+
Soft
Start
Ramp
OPP COMP
PWM COMP
120−ns
LEB
DRV
+
Short Circuit COMP
1.2 V
Overload detection block
Abnormal Over−current fault (CSStop)
0.2 V (Without IFF pin)
VIFF/4 (With IFF pin)
Ropp1
Rfb
Vdd
Current Sense and Associated Protections
The feedback voltage (V
FB
) is internally divided by K
FB
(K
FB
=4, typically) to form the current setpoint. The power
switch on time is modulated by comparing a ramp
proportional to the switch current to V
FB
/K
FB
using the
PWM Comparator. The switch current is sensed across a
current sense resistor, R
SENSE
and the resulting voltage is
applied to the CS pin. The current sense signal is blanked by
a leading edge blanking (LEB) circuit. The blanking period
eliminates the leading edge spike and high frequency noise
during the switch turn−on event. The LEB period, t
CS(LEB1)
,
is typically 275 ns. The drive pulse terminates once the
current sense signal exceeds V
FB
/K
FB
.
The Maximum Peak Current Comparator compares the
current sense signal to a reference voltage to limit the
maximum peak current of the system. The maximum peak
current reference voltage, V
ILIM1
, is typically 0.8 V. The
maximum peak current setpoint is reduced by the overpower
compensation (OPP) circuitry. In case, a wrong OPP signal
is applied to the circuit, a second comparator to V
ILIM1
is
placed to get sure that the current setpoint is at least limited
to V
ILIM1.
An overload condition causes the output of one of
the Maximum Peak Current Comparators to transition high
and enable the overload timer. Figure 57 shows the
implementation of the current sensing circuitry.

NCP1339EDR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers HIGH VOLTAGE QUASI RES CONTROLLER
Lifecycle:
New from this manufacturer.
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