NCP1339
www.onsemi.com
30
A 2
nd
Over−Current Comparator for Abnormal
Overcurrent Fault Detection
A severe fault like a winding short−circuit can cause the
switch current to increase very rapidly during the on−time.
The current sense signal significantly exceeds V
ILIM1
. But,
because the current sense signal is blanked by the LEB
circuit during the switch turn on, the power switch current
can become huge causing system damage.
The NCP1339 protects against this fault by adding an
additional comparator for Abnormal Overcurrent Fault
detection. The current sense signal is blanked with a shorter
LEB duration, t
CS(LEB2)
, typically 125 ns, before applying
it to the Abnormal Overcurrent Fault Comparator. The
voltage threshold of the comparator, V
ILIM2
, typically 1.2 V,
is set 50% higher than V
ILIM1
, to avoid interference with
normal operation. Four consecutive Abnormal Overcurrent
faults cause the controller to enter latch mode (NCP1339D,
E, F and I versions) or auto−recovery (NCP1339C, G, H and
J). The count to 4 provides noise immunity during surge
testing. The counter is reset each time a DRV pulse occurs
without activating the Fault Overcurrent Comparator.
Protecting from a Failure of the Current Sensing
A 1−mA (typically) pull−up current source, I
CS
, pulls up
the CS pin to disable the controller if the pin is left open.
In addition the maximum on−time (32 ms typically) avoids
that the MOSFET stays permanently on if the switch current
cannot reach the current setpoint when for instance, the input
voltage is low.
Soft−Start
Soft−start is achieved by ramping up an internal reference,
V
SSTART
, and comparing it to current sense signal. V
SSTART
ramps up from 0 V once the controller powers up. The
setpoint rise is then limited by the V
SSTART
ramp so that a
gradual increase of the power switch current during
start−up. The soft−start duration (that is, the time necessary
for the ramp to reach the V
ILIM1
steady state current limit),
t
SSTART
, is typically 4 ms.
During soft−start the ZCD timeout duration is extended.
This is because, during startup, demagnetization phases are
long and difficult to detect since the auxiliary winding
voltage is small. In this condition, the 6−ms steady−state
timeout is generally shorter than the inductor
demagnetization period and if used to restart a switching
cycle, it can cause continuous current mode (CCM)
operation for few cycles until the voltage on the ZCD pin is
high enough for proper valleys detection. A longer timeout
period, t
(out1)
, (typically 100 ms) is therefore set during
soft−start to prevent CCM operation.
Also, the Fault comparator to 0.4 V (or OTP comparator
since typically used for overtemperature) is blanked for the
soft−start duration. The pin can then be filtered by an
external capacitor.
Jittering Capability
In order to help meet the EMI requirements, the NCP1339
(E, F, G, I and J versions) features the jittering capability to
average the spectrum rays over the frequency range. The
function consists of sourcing a 0 to 100 mA, 1.3 kHz
triangular current out of the CS pin (I
JIT
). This current
together with the external resistor placed on the CS pin
generates an offset that will change the actual power switch
peak current and hence the operation frequency.
The jittering current source and hence the jittering
function is enabled only in high line condition since at low
line, the input voltage ripple is generally sufficient to help
meet EMI specs. This function is also disabled in Frequency
Foldback operation mode.
The jittering function modulates the peak current level. As
a result, the FB signal that struggles for compensating this
effect and limiting the output voltage ripple, exhibits a
swing. The resistor placed between the CS pin and the
current sense resistor must not be too high. Otherwise, the
jittering offset on the CS pin can lead to a FB swing
exceeding the VLO mode 600 mV hysteresis inbuilt to avoid
unwanted transitions between valleys. In practice, this
resistor is generally below 1 kohm.
Driver
The NCP1339 maximum supply voltage, V
CC(max)
, is
28 V. Typical high−voltage MOSFETs have a maximum
gate voltage rating of 20 V. The DRV pin incorporates an
active voltage clamp to limit the gate voltage on the external
MOSFETs. The DRV voltage clamp, V
DRV(high)
is typically
12 V with a maximum limit of 14 V.
Thermal Shutdown
An internal thermal shutdown circuit monitors the
junction temperature of the IC. The controller is disabled if
the junction temperature exceeds the thermal shutdown
threshold, T
SHDN
, typically 150°C. A continuous V
CC
hiccup is initiated after a thermal shutdown fault is detected.
The controller restarts at the next V
CC(on)
once the IC
temperature drops below T
SHDN
by the thermal shutdown
hysteresis, T
SHDN(HYS)
, typically 40°C.
The thermal shutdown is also cleared if V
CC
drops below
V
CC(reset)
, a brown−out fault is detected or if the controller
enters power savings mode. A new power up sequences
commences at the next V
CC(on)
once all the faults are
removed.
