AD5370BSTZ Datasheet AD5370BSTZ, EVAL-AD5370EBZ, AD5370BSTZ-REEL | P19-P21

AD5370

Rev. 0 | Page 18 of 28

Reference Selection Example

• Nominal Output Range = 12 V (−4 V to +8 V)

• Zero-Scale Error = ±70 mV

• Gain Error = ±3%

• SIGGND = AGND = 0 V

Then

• Gain Error = ±3%

=> Maximum Positive Gain Error = +3%

=> Output Range Including Gain Error = 12 + 0.03(12) =

12.36 V

• Offset Error = ±70 mV

=> Maximum Offset Error Span = 2(70 mV) = 0.14 V

=> Output Range Including Gain Error and Offset Error =

12.36 V + 0.14 V = 12.5 V

• VREF Calculation

Actual Output Range = 12.5 V, that is, −4.25 V to +8.25 V;

VREF = (8.25 V + 4.25 V)/4 = 3.125 V

If the equation yields an inconvenient reference level, the user

can adopt one of the following approaches:

• Use a resistor divider to divide down a convenient, higher

reference level to the required level.

• Select a convenient reference level above VREF, and modify

the gain and offset registers to downsize the reference digitally.

In this way, the user can use almost any convenient reference

level but may reduce the performance by overcompaction

of the transfer function.

• Use a combination of these two approaches.

CALIBRATION

The user can perform a system calibration on the AD5370 to

reduce gain and offset errors to below 1 LSB. This is achieved

by calculating new values for the M and C registers and reprogram-

ming them.

Reducing Zero-Scale Error

Zero-scale error can be reduced as follows:

1. Set the output to the lowest possible value.

2. Measure the actual output voltage and compare it with the

required value. This gives the zero-scale error.

3. Calculate the number of LSBs equivalent to the error and

add this from the default value of the C register. Note that

only negative zero-scale error can be reduced.

Reducing Full-scale Error

Full-scale error can be reduced as follows:

1. Measure the zero-scale error.

2. Set the output to the highest possible value.

3. Measure the actual output voltage and compare it with the

required value. Add this error to the zero-scale error. This

is the span error, which includes the full-scale error.

4. Calculate the number of LSBs equivalent to the full-scale

error and subtract it from the default value of the M register.

Note that only positive full-scale error can be reduced.

5. The M and C registers should not be programmed until

both zero-scale and full-scale errors have been calculated.

AD5370 Calibration Example

This example assumes that a −4 V to +8 V output is required.

The DAC output is set to −4 V but measured at −4.03 V. This

gives a zero-scale error of −30 mV.

1. 1 LSB = 12 V/65,536 = 183.11 μV

2. 30 mV = 164 LSB

The full-scale error can now be calculated. The output is set to

+8 V and a value of +8.02 V is measured. The full-scale error is

+20 mV – (–30 mV) = +50 mV.

50 mV = 273 LSBs

The errors can now be removed.

1. 164 LSB should be added to the default C register value,

that is (32,768 + 164) = 32,932.

2. 273 LSB should be subtracted from the default M register

value; that is, (65,535 − 273) = 65,262.

3. 65,262 should be programmed to the M register and 32,932

should be programmed to the C register.

ADDITIONAL CALIBRATION

The techniques described in the previous section are usually

enough to reduce the zero-scale and full-scale errors in most

applications. However, there are limitations whereby the errors

may not be sufficiently removed. For example, the offset (C)

negative zero-scale error. A positive offset cannot be reduced.

Likewise, if the maximum voltage is below the ideal value, that

is, a negative full-scale error, the gain (M) register cannot be

used to increase the gain to compensate for the error.

These limitations can be overcome by increasing the reference

value. With a 3 V reference, a 12 V span is achieved. The ideal

voltage range for the AD5370 is −4 V to +8 V. Using a 3.1 V

reference increases the range to −4.133 V to +8.2667 V. Clearly,

in this case, the offset and gain errors are insignificant, and the

M and C registers can be used to raise the negative voltage to

−4 V and then reduce the maximum voltage to +8 V to give the

most accurate values possible.

AD5370

Rev. 0 | Page 19 of 28

RESET FUNCTION

The reset function is initiated by the

RESET

pin. On the rising

edge of

RESET

, the AD5370 state machine initiates a reset

sequence to reset the X, M, and C registers to their default

values. This sequence typically takes 300 μs, and the user should

not write to the part during this time. On power-up, it is recom-

mended that the user bring

RESET

high as soon as possible to

properly initialize the registers.

When the reset sequence is complete (and provided that

CLR

high), the DAC output is at a potential specified by the default

outputs remain at SIGGNDx until the X, M, or C register is

updated and

LDAC

is taken low. The AD5370 can be returned

to the default state by pulsing

RESET

low for at least 30 ns. Note

that, because the reset function is triggered on the rising edge,

bringing

RESET

low has no effect on the operation of the AD5370.

CLEAR FUNCTION

CLR

is an active low input that should be high for normal

operation. The

CLR

pin has in internal 500 kΩ pull-down

resistor. When

CLR

is low, the input to each of the DAC output

buffer stages, VOUT0 to VOUT39, is switched to the externally

set potential on the relevant SIGGND pin. While

CLR

is low, all

LDAC

pulses are ignored. When

CLR

is taken high again, the

DAC outputs remain cleared until

LDAC

is taken low. The contents

of the input registers and DAC registers are not affected by taking

CLR

low. To prevent glitches from appearing on the outputs,

CLR

should be brought low by writing to the offset DAC whenever

the output span is adjusted.

BUSY AND LDAC FUNCTIONS

The value of an X2 (A or B) register is calculated each time the

user writes new data to the corresponding X1, C, or M register.

During the calculation of X2, the

BUSY

output goes low. While

BUSY

is low, the user can continue writing new data to the X1,

M, or C register (see the

details), but no DAC output updates can take place.

The

BUSY

pin is bidirectional and has a 50 kΩ internal pull-up

resistor. In cases where multiple AD5370 devices are used in

one system, the

BUSY

pins can be tied together. This is useful

when it is required that no DAC channel in any device be

updated until all other DAC channels are ready to be updated.

When each device finishes updating the X2 (A or B) register, it

releases the

BUSY

pin. If another device has not finished

updating its X2 register, it holds

BUSY

low, thus delaying the

effect of

LDAC

going low.

The DAC outputs are updated by taking the

LDAC

input low. If

LDAC

goes low while

BUSY

is active, the

LDAC

event is stored

and the DAC outputs update immediately after

BUSY

goes

high. A user can also hold the

LDAC

input permanently low. In

this case, the DAC outputs update immediately after

BUSY

goes

high. Whenever the

/B select registers are written to,

BUSY

also goes low, for approximately 600 ns.

The AD5370 has flexible addressing that allows writing of data

to a single channel, all channels in a group, the same channel in

Group 0 to Group 4 or the same channel in Group 1 to Group 4,

or all channels in the device. This means that 1, 4, 5, 8, or 40

DAC register values may need to be calculated and updated.

Because there is only one multiplier shared among 40 channels,

this task must be done sequentially so that the length of the

BUSY

pulse varies according to the number of channels being

updated.

Table 8.

BUSY

Pulse Widths

Action

BUSY

Pulse Width

(μs max)

Loading X1A, X1B, C, or M to 1 channel

1.5

Loading X1A, X1B, C, or M to 4 channels 3.3

Loading X1A, X1B, C, or M to 5 channels 3.9

Loading X1A, X1B, C, or M to 8 channels 5.7

Loading X1A, X1B, C, or M to 40 channels 24.9

BUSY

Pulse Width = ((Number of Channels + 1) × 600 ns) + 300 ns.

A single channel update is typically 1 µs.

The AD5370 contains an extra feature whereby a DAC register

is not updated unless its X2A or X2B register has been written

to since the last time

LDAC

was brought low. Normally, when

LDAC

is brought low, the DAC registers are filled with the

contents of the X2A or X2B register, depending on the setting of

the

/B select registers. However, the AD5370 updates the DAC

unnecessary digital crosstalk.

POWER-DOWN MODE

The AD5370 can be powered down by setting Bit 0 in the

control register to 1. This turns off the DAC channels, thus

reducing the current consumption. The DAC outputs are

connected to their respective SIGGND potentials. The power-

down mode does not change the contents of the registers, and

the DAC channels return to their previous voltage when the

power-down bit is cleared to 0.

THERMAL SHUTDOWN FUNCTION

The AD5370 can be programmed to power down the DACs if

the temperature on the die exceeds 130°C. Setting Bit 1 in the

control register to 1 (see the

Special Function Mode section)

enables this function. If the die temperature exceeds 130°C, the

AD5370 enters a temperature power-down mode, which is

equivalent to setting the power-down bit in the control register.

To indicate that the AD5370 has entered temperature shutdown

mode, Bit 4 of the control register is set to 1. The AD5370 remains

in temperature shutdown mode, even if the die temperature

falls, until Bit 1 in the control register is cleared to 0.

AD5370

Rev. 0 | Page 20 of 28

TOGGLE MODE

The AD5370 has two X2 registers per channel, X2A and X2B,

that can be used to switch the DAC output between two levels

with ease. This approach greatly reduces the overhead required

by a microprocessor that would otherwise have to write to each

channel individually. When the user writes to the X1A, X2A, M,

or C register, the calculation engine takes a certain amount of

time to calculate the appropriate X2A or X2B value. If the

application only requires that the DAC output switch between

two levels, as is the case with a data generator, any method that

reduces the amount of calculation time necessary is advantageous.

For the data generator example, the user need only set the high

and low levels for each channel once by writing to the X1A and

X1B registers. The values of X2A and X2B are calculated and

stored in their respective registers. The calculation delay

therefore happens only during the setup phase, that is, when

programming the initial values. To toggle a DAC output

between the two levels, it is only required to write to the

relevant

/B select register to set the MUX2 register bit. Further-

more, because there are eight MUX2 control bits per register, it

is possible to update eight channels with a single write.

Table 15

shows the bits that correspond to each DAC output.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P29

AD5370BSTZ

Mfr. #:

Buy AD5370BSTZ

Manufacturer:

Analog Devices Inc.

Description:

Digital to Analog Converters - DAC 40-CH 16-bit Serial bipolar IC

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

AD5370BSTZ

AD5370BSTZ

Products related to this Datasheet