AD5370
Rev. 0 | Page 3 of 28
GENERAL DESCRIPTION
The AD5370
1
contains forty 16-bit DACs in a single 64-lead
LFCSP and a 64-lead LQFP. The device provides buffered
voltage outputs with a span that is 4× the reference voltage. The
gain and offset of each DAC channel can be independently
trimmed to remove errors. For even greater flexibility, the device is
divided into five groups of eight DACs. Three offset DAC channels
allow the output range of blocks to be adjusted. Group 0 can be
adjusted by Offset DAC 0, Group 1 can be adjusted by Offset
DAC 1, and Group 2 to Group 4 can be adjusted by Offset DAC 2.
The AD5370 offers guaranteed operation over a wide supply
range, with V
SS
from −16.5 V to −4.5 V and V
DD
from +9 V to
+16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.
1
Protected by U.S. Patent No. 5,969,657; other patents pending.
The AD5370 has a high speed serial interface that is compatible
with SPI, QSPI™, MICROWIRE™, and DSP interface standards
and can handle clock speeds of up to 50 MHz.
The DAC registers are updated on receipt of new data. All the
outputs can be updated simultaneously by taking the
LDAC
input low. Each channel has a programmable gain and an offset
adjust register to allow removal of gain and offset errors.
Each DAC output is gained and buffered on chip with respect to
an external SIGGNDx input. The DAC outputs can also be
switched to SIGGNDx via the
CLR
pin.
Table 1. High Channel Count Bipolar DACs
Model Resolution Nominal Output Span Output Channels Linearity Error (LSB)
AD5360 16 bits 4 × V
REF
(20 V) 16 ±4
AD5361 14 bits 4 × V
REF
(20 V) 16 ±1
AD5362 16 bits 4 × V
REF
(20 V) 8 ±4
AD5363 14 bits 4 × V
REF
(20 V) 8 ±1
AD5370 16 bits 4 × V
REF
(12 V) 40 ±4
AD5371 14 bits 4 × V
REF
(12 V) 40 ±1
AD5372 16 bits 4 × V
REF
(12 V) 32 ±4
AD5373 14 bits 4 × V
REF
(12 V) 32 ±1
AD5378 14 bits ±8.75 V 32 ±3
AD5379 14 bits ±8.75 V 40 ±3
