AD5370
Rev. 0 | Page 6 of 28
TIMING CHARACTERISTICS
DV
CC
= 2.5 V to 5.5 V; V
DD
= 9 V to 16.5 V; V
SS
= −16.5 V to −4.5 V; V
REF
= 3 V; AGND = DGND = SIGGND = 0 V; C
L
= 200 pF to GND;
R
L
= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4. SPI Interface
Limit at T
MIN
, T
MAX
Parameter
1, 2, 3
Min Typ Max
Unit Description
t
1
20 ns SCLK cycle time
t
2
8 ns SCLK high time
t
3
8 ns SCLK low time
t
4
11 ns
SYNC
falling edge to SCLK falling edge setup time
t
5
20 ns
Minimum SYNC
high time
t
6
10 ns
24
th
SCLK falling edge to SYNC rising edge
t
7
5 ns Data setup time
t
8
5 ns Data hold time
t
9
4
42 ns
SYNC
rising edge to BUSY falling edge
t
10
1.5 μs
BUSY
pulse width low (single-channel update); see Table 8
t
11
600 ns Single-channel update cycle time
t
12
20 ns
SYNC
rising edge to LDAC falling edge
t
13
10 ns
LDAC
pulse width low
t
14
3 μs
BUSY
rising edge to DAC output response time
t
15
0 ns
BUSY
rising edge to LDAC falling edge
t
16
3 μs
LDAC
falling edge to DAC output response time
t
17
20 30 μs DAC output settling time
t
18
140 ns
CLR
/RESET pulse activation time
t
19
30 ns
RESET
pulse width low
t
20
400 μs
RESET
time indicated by BUSY low
t
21
270 ns
Minimum SYNC
high time in readback mode
t
22
5
25 ns SCLK rising edge to SDO valid
t
23
80 ns
RESET
rising edge to BUSY falling edge
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
R
= t
F
= 2 ns (10% to 90% of DV
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 4 and Figure 5.
4
This is measured with the load circuit shown in Figure 2.
5
This is measured with the load circuit shown in Figure 3.
TIMING DIAGRAMS
TO
OUTPUT
PIN
C
L
50pF
R
L
2.2k
Ω
V
OL
DV
CC
05813-002
V
OH
(MIN) – V
OL
(MAX)
2
200µA I
OL
200µA I
OH
O OUTPUT
PIN
C
L
50pF
5813-003
Figure 2. Load Circuit for
BUSY
Timing Diagram
Figure 3. Load Circuit for SDO Timing Diagram
