Products and specifications discussed herein are subject to change by Micron without notice.
4Gb: x4, x8 TwinDie DDR3 SDRAM
Functionality
PDF: 09005aef83188bab/Source: 09005aef83169de6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN
1 ©2008 Micron Technology, Inc. All rights reserved.
TwinDie
TM
DDR3 SDRAM
MT41J1G4 – 64 Meg x 4 x 8 Banks x 2 Ranks
MT41J512M8 – 32 Meg x 8 x 8 Banks x 2 Ranks
For component data sheets, refer to Micron’s Web site: www.micron.com
Functionality
The 4Gb TwinDie™ DDR3 SDRAM uses Micron’s 2Gb
DDR3 die and has similar functionality. This data sheet
includes key timing parameters, ball assignments, a
functional description, functional block diagrams,
IDD specifications, and package dimensions. Refer to
Micron’s 2Gb DDR3 SDRAM data sheet for complete
specifications. (Specifications for base part number
MT41J512M4 correlate to TwinDie manufacturing part
number MT41J1G4; specifications for base part num-
ber MT41J256M8 correlate to TwinDie manufacturing
part number MT41J512M8.)
Features
• Uses 2Gb Micron die
• Two ranks (includes dual CS#, ODT, CKE, and
ZQ balls)
• Each rank has 8 internal banks
•V
DD
= V
DDQ
= +1.5V ±0.075V
• 1.5V center-terminated push/pull I/O
• JEDEC-standard ball-out
•Low-profile package
•T
C
of 0°C to 95°C
– 0°C to 85°C: 8192 refresh cycles in 64ms
– 85°C to 95°C: 8192 refresh cycles in 32ms
Notes: 1. CL = CAS (READ) latency.
Options Marking
• Configuration
– 64 Meg x 4 x 8 banks x 2 ranks 1G4
– 32 Meg x 8 x 8 banks x 2 ranks 512M8
• FBGA package (lead-free)
– 82-ball FBGA (12.5 x 15 x 1.35mm)
Rev. A
THU
– 78-ball FBGA (9 x 11.5 x 1.2mm)
Rev. D
THD
• Timing – cycle time
1
– 1.5ns @ CL = 10 (DDR3-1333) -15
– 1.5ns @ CL = 9 (DDR3-1333) -15E
– 1.87ns @ CL = 8 (DDR3-1066) -187
– 1.87ns @ CL = 7 (DDR3-1066) -187E
– 2.5ns @ CL = 6 (DDR3-800) -25
– 2.5ns @ CL = 5 (DDR3-800) -25E
• Self refresh
– Standard None
• Operating temperature
– Commercial (0°C
≤
T
C
≤
95°C
)
None
• Revision (82-ball FBGA) :A
• Revision (78-ball FBGA) :D
Table 1: Key Timing Parameters
Speed Grade Data Rate (MT/s) Target
t
RCD-
t
RP-CL
t
RCD (ns)
t
RP (ns) CL (ns)
-15 1333 10-10-10 15 15 15
-15E 1333 9-9-9 13.5 13.5 13.5
-187 1066 8-8-8 15 15 15
-187E 1066 7-7-7 13.1 13.1 13.1
-25 800 6-6-6 15 15 15
-25E 800 5-5-5 12.5 12.5 12.5
