MT41J512M8THD-187E:D

PDF: 09005aef83188bab/Source: 09005aef83169de6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN
7 ©2008 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR3 SDRAM
Functional Description
Functional Description
The 4Gb (TwinDie) DDR3 SDRAM is a high-speed, CMOS dynamic random access mem-
ory device containing 4,294,967,296 bits and is internally configured as two 8-bank 2Gb
DDR3 SDRAM.
Although each die is tested individually within the dual-die package, some TwinDie test
results may vary from a like-die tested within a monolithic die package.
The DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or write
access consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal
DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at
the I/O balls.
The differential data strobes (DQS, DQS#) are transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
Read and write accesses to the DDR3 SDRAM are burst oriented. Accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVATE command are used to select the bank and row to be accessed. The address
bits (including CSn#, BAn, and An) registered coincident with the READ or WRITE com-
mand are used to select the rank, bank, and starting column location for the burst
access.
This data sheet provides a general description, package dimensions, and the package
ballout. Refer to the Micron 2Gb DDR3 data sheet for complete information regarding
individual die initialization, register definition, command descriptions, and die opera-
tion.
PDF: 09005aef83188bab/Source: 09005aef83169de6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN
8 ©2008 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR3 SDRAM
Functional Block Diagrams
Functional Block Diagrams
Figure 3: Functional Block Diagram (64 Meg x 4 x 8 Banks x 2 Ranks)
Figure 4: Functional Block Diagram (32 Meg x 8 x 8 Banks x 2 Ranks)
RAS#
CAS#
WE#
RESET#
CK
CK#
DQ[3:0]
DQS, DQS#
DM
A[14:0],
BA[2:0]
CS0#
CKE0
ODT0
Rank 0
(64 Meg x 4 x 8 banks)
Rank 1
(64 Meg x 4 x 8 banks)
CS1#
CKE1
ODT1
ZQ1
ZQ0
TDQS#
CAS#
RAS#
WE#
CK
CK#
DQ[7:0]
DQS, DQS#
DM/TDQS
A[14:0],
BA[2:0]
Rank 0
(32 Meg x 8 x 8 banks)
Rank 1
(32 Meg x 8 x 8 banks)
CS0#
CKE0
ODT0
ZQ0
CS1#
CKE1
ODT1
ZQ1
RESET#
PDF: 09005aef83188bab/Source: 09005aef83169de6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT41J1G4_64M_32M_twindie.fm - Rev. F 11/09 EN
9 ©2008 Micron Technology, Inc. All rights reserved.
4Gb: x4, x8 TwinDie DDR3 SDRAM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
outside those indicated in the device data sheet is not implied. Exposure to absolute
maximum rating conditions for extended periods may adversely affect reliability.
Notes: 1. V
DD
and V
DDQ
must be within 300mV of each other at all times, and V
REF
must not be
greater than 0.6 × V
DDQ
. When V
DD
and V
DDQ
are less than 500mV, V
REF
may be 300mV.
2. The minimum limit requirement is for testing purposes. The leakage current on the V
REF
pin should be minimal.
3. MAX operating case temperature. T
C
is measured in the center of the package (see
Figure 5 on page 10).
4. Device functionality is not guaranteed if the DRAM device exceeds the maximum T
C
dur-
ing operation.
Temperature and Thermal Impedance
It is imperative that the DDR3 SDRAM devices temperature specifications, shown in
Table 5 on page 10, be maintained to ensure the junction temperature is in the proper
operating range to meet data sheet specifications. An important step in maintaining the
proper junction temperature is using the devices thermal impedances correctly. Ther-
mal impedances listed in Table 6 on page 10 apply to the current die revision and pack-
ages.
Incorrectly using thermal impedances can produce significant errors. Read Micron tech-
nical note TN-00-08: “Thermal Applications, prior to using the thermal impedances in
Table 6. For designs that are expected to last several years and require the flexibility to
use several DRAM die shrinks, consider using final target theta values (rather than exist-
ing values) to account for increased thermal impedances from the reduction in die size.
The DDR3 SDRAM devices safe junction temperature range can be maintained when
the T
C
specification is not exceeded. In applications where the devices ambient temper-
ature is too high, use of forced air and/or heat sinks may be required to satisfy the case
temperature specifications.
Table 4: Absolute Maximum Ratings
Symbol Parameter Min Max Units Notes
V
DD
V
DD
supply voltage relative to V
SS
–0.4 1.975 V 1
V
DDQ
V
DD
supply voltage relative to V
SSQ
–0.4 1.975 V
V
IN
, V
OUT
Voltage on any ball relative to V
SS
–0.4 1.975 V
I
I
Input leakage current
Any input 0V V
IN
V
DD
,
V
REF
pin 0V V
IN
1.1V
(All other pins not under test = 0V)
–4 +4 µA
I
VREF
V
REF
supply leakage current
V
REFDQ
= V
DD
/2 or V
REFCA
= V
DD
/2
(All other pins not under test = 0V)
–2 +2 µA 2
T
C
Operating case temperature
095°C3, 4
T
STG
Storage temperature
–55 150 °C

MT41J512M8THD-187E:D

Mfr. #:
Manufacturer:
Micron
Description:
IC DRAM 4G PARALLEL 78FBGA
Lifecycle:
New from this manufacturer.
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