8761I Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 25, 20162
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
1 REF_CLK Input Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
2, 16, 17, 21,
25, 29, 33, 48,
52, 56, 60, 64
GND Power Power supply ground.
3, 4 XTAL1, XTAL2 Input Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
5, 9, 40, 44 V
DD
Power Core supply pins.
6 XTAL_SEL Input Pullup
Selects between crystal oscillator or reference clock as the PLL refer-
ence source. Selects XTAL inputs when HIGH. Selects REF_CLK when
LOW. LVCMOS / LVTTL interface levels.
7 PLL_SEL Input Pullup
Selects between PLL and bypass mode. When HIGH, selects PLL.
When LOW, selects reference clock. LVCMOS / LVTTL interface levels.
8V
DDA
Power Analog supply pin. See Applications Note for fi ltering.
10, 11
D_SELC0,
D_SELC1
Input Pulldown
Selects divide value for Bank C outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
12 OEC Input Pullup
Determines state of Bank C outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
13 OEA Input Pullup
Determines state of Bank A outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
14, 15
D_SELA0,
D_SELA1
Input Pulldown
Selects divider value for Bank A outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
18, 20,
22, 24
QA0, QA1,
QA2, QA3
Output
Bank A clock outputs. 15
Ω typical output impedance.
LVCMOS / LVTTL interface levels.
19, 23 V
DDOA
Power Output supply pins for Bank A outputs.
26, 28,
30, 32
QB0, QB1,
QB2, QB3
Output
Bank B clock outputs. 15
Ω typical output impedance.
LVCMOS / LVTTL interface levels.
27, 31 V
DDOB
Power Output supply pins for Bank B outputs.
34, 35
D_SELB1,
D_SELB0
Input Pulldown
Selects divider value for Bank B outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
36 OEB Input Pullup
Determines state of Bank B outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
37 OED Input Pullup
Determines state of Bank D outputs. When HIGH, outputs are enabled.
When LOW, outputs are disabled. LVCMOS / LVTTL interface levels.
38, 39
D_SELD1,
D_SELD0
Input Pulldown
Selects divider value for Bank D outputs as described in Table 3.
LVCMOS / LVTTL interface levels.
41 MR Input Pulldown
Active HIGH Master reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the
internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
42 FBDIV_SEL1 Input Pulldown
Selects divider value for bank feedback output as described in Table 3.
LVCMOS / LVTTL interface levels.
43 FBDIV_SEL0 Input Pullup
Selects divider value for bank feedback output as described in Table 3.
LVCMOS / LVTTL interface levels.
45 FB_IN Input Pulldown
Feedback input to phase detector for generating clocks with
“zero delay”. LVCMOS / LVTTL interface levels.
