8761CYILF Datasheet 8761CYILF, 8761CYILFT | P10-P12

8761I Data Sheet

INPUTS:

CRYSTAL INPUT:

For applications not requiring the use of the crystal oscillator

input, both XTAL_IN and XTAL_OUT can be left ﬂ oating. Though

not required, but for additional protection, a 1kΩ resistor can be

tied from XTAL_IN to ground.

REF_CLK I

NPUT:

For applications not requiring the use of the reference clock,

it can be left ﬂ oating. Though not required, but for additional

protection, a 1kΩ resistor can be tied from the REF_CLK to

ground.

LVCMOS C

ONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

OUTPUTS:

LVCMOS OUTPUT:

All unused LVCMOS output can be left ﬂ oating. We recommend

that there is no trace attached.

8761I Data Sheet

SCHEMATIC EXAMPLE

Figure 3 shows a schematic example of the 8761I. In this

example, the input is driven by an 18pF parallel crystal. The de-

coupling capacitors should be physically located near the power

pin. For 8761I, the unused clock outputs can be left ﬂ oating. The

optional C1 and C2 are spare footprints for frequency ﬁ ne tuning.

FIGURE 3. 8761I CLOCK GENERATOR SCHEMATIC EXAMPLE

(U1,44)

C9

0.1u

(U1,62)

C14

0.1u

C11

0.1u

C16

10u

Receiv er

Zo = 50

(U1,58)

R5

1K

VDDO=3.3V

(U1,46)

C7

0.1u

(U1,54)

VDD

SP = Spare, Not Install

VDD

C10

0.1u

C6

0.1u

VDD=3.3V

R3

36

VDD

Receiv er

Set Logic

Input to '1'

RD2

1K

(U1,9)

R1

36

Receiv er

Zo = 50

R4

36

To Logic

Input pins

C12

0.1u

X1

25MHz,18pF

C4

0.1u

R2

36

RU1

1K

VDDO

C2

SP

Zo = 50

C17

0.1u

R6

1K

(U1,19)

U1

ICS8761

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

39

38

37

36

35

34

33

32

31

30

29

28

27

52

51

50

49

48

47

46

45

44

43

42

41

40

63

62

61

60

59

58

57

56

55

54

53

64

REF_CLK

GND

XTAL 1

XTAL 2

VDD

XTAL_SEL

PLL_SEL

VDDA

VDD

D_SELC0

D_SELC1

OEC

OEA

D_SELA0

D_SELA1

GND

QA0

VDDOA

QA1

GND

QA2

VDDOA

QA3

GND

QB0

D_SELD0

D_SELD1

OED

OEB

D_SELB0

D_SELB1

GND

QB3

VDDOB

QB2

GND

QB1

VDDOB

GND

QD2

VDDOD

QD3

GND

FB_OUT

VDDOFB

FB_IN

VDD

FBDIV_SEL0

FBDIV_SEL1

MR

VDD

QC0

VDDOC

QC1

GND

QC2

VDDOC

QC3

GND

QD0

VDDOD

QD1

GND

Set Logic

Input to '0'

VDDO

C8

0.1u

VDD

(U1,40)

C15

0.1u

To Logic

Input pins

C5

0.1u

(U1,23)

C3

0.1u

VDDO

RU2

SP

VDD

Logic Input Pin Examples

(U1,27) (U1,31)

VDD

FB

C13

0.1u

C1

SP

(U1,5)

Receiv er

RD1

SP

VDDO

Zo = 50

(U1,50)

ICS8761I

8761I Data Sheet

TRANSISTOR COUNT

The transistor count for 8761I is: 6040

TABLE 8. θ

JA

VS. AIR FLOW TABLE FOR 64 LEAD LQFP

θ

JA

by Velocity (Linear Feet per Minute)

0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 58.8°C/W 48.5°C/W 43.2°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 41.1°C/W 35.8°C/W 33.6°C/W

NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.

RELIABILITY INFORMATION

8761CYILF

8761CYILF

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