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8761CYILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
8761I Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 25, 20164
TABLE 3D. CONTROL FUNCTION TABLE
TABLE 3E. CONTROL FUNCTION TABLE (PCI CONFIGURATION)
Inputs
Outputs
PLL_SEL = 1 Frequency
D_SELx1 D_SELx0 FBDIV_SEL1 FBDIV_SEL0
Reference Frequency
(MHz)
QX0:QX3
QX0:QX3
(MHz)
FB_OUT
(MHz)
0 0 0 0 66.67 x 2 133 66.67
0 0 0 1 33.33 x 4 133 33.33
0 0 1 0 25 x 5.33 133 25
0 0 1 1 20 x 6.67 133 20
0 1 0 0 66.67 x 1.5 100 66.67
0 1 0 1 33.33 x 3 100 33.33
0 1 1 0 25 x 4 100 25
0 1 1 1 20 x 5 100 20
1 0 0 0 66.67 x 1 66.67 66.67
1 0 0 1 33.33 x 2 66.67 33.33
1 0 1 0 25 x 2.67 66.67 25
1 0 1 1 20 x 3.33 66.67 20
1 1 0 0 66.67 ÷ 2 33.33 66.67
1 1 0 1 33.33 ÷ 1 33.33 33.33
1 1 1 0 25 x 1.33 33.33 25
1 1 1 1 20 x 1.67 33.33 20
NOTE: D_SELx1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELx0 denotes D_SELA0, D_SELB0, D_
SELC0, and D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
Inputs
Outputs
PLL_SEL =1 Frequency
D_SELx1 D_SELx0 FBDIV_SEL1 FBDIV_SEL0
Reference Fre-
quency Range
(MHz)
QX0:QX3 QX0:QX3 (MHz)
FB_OUT
(MHz)
0 0 0 0 41.6 - 83.33 x 2 83.33 - 166.67 41.6 - 83.33
0 0 0 1 20.83 - 41.67 x 4 83.33 - 166.67 20.83 - 41.67
0 0 1 0 15.62 - 31.25 x 5.33 83.33 - 166.67 15.62 - 31.25
0 0 1 1 12.5 - 25 x 6.67 83.33 - 166.67 12.5 - 25
0 1 0 0 41.6 - 83.33 x 1.5 62.4 - 125 41.6 - 83.33
0 1 0 1 20.83 - 41.67 x 3 62.4 - 125 20.83 - 41.67
0 1 1 0 15.62 - 31.25 x 4 62.4 - 125 15.62 - 31.25
0 1 1 1 12.5 - 25 x 5 62.4 - 125 12.5 - 25
1 0 0 0 41.6 - 83.33 x 1 41.6 - 83.33 41.6 - 83.33
1 0 0 1 20.83 - 41.67 x 2 41.6 - 83.33 20.83 - 41.67
1 0 1 0 15.62 - 31.25 x 2.67 41.6 - 83.33 15.62 - 31.25
1 0 1 1 12.5 - 25 x 3.33 41.6 - 83.33 12.5 - 25
1 1 0 0 41.6 - 83.33 ÷ 2 20.8 - 41.67 41.6 - 83.33
1 1 0 1 20.83 - 41.67 ÷ 1 20.8 - 41.67 20.83 - 41.67
1 1 1 0 15.62 - 31.25 x 1.33 20.8 - 41.67 15.62 - 31.25
1 1 1 1 12.5 - 25 x 1.67 20.8 - 41.67 12.5 - 25
NOTE: D_SELX1 denotes D_SELA1, D_SELB1, D_SELC1, and D_SELD1. D_SELX0 denotes D_SELA0, D_SELB0, D_
SELC0, and D_SELD0. QX0:QX3 denotes QA0:QA3, QB0:QB3, QC0:QC3, and QD0:QD3.
8761I Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 25, 20165
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDA
= V
DDOX
= 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDA
Analog Supply Voltage 3.135 3.3 3.465 V
V
DDOx
Output Supply Voltage; NOTE 1
3.135 3.3 3.465 V
2.375 2.5 2.625 V
I
DD
Power Supply Current 175 mA
I
DDA
Analog Supply Current 55 mA
I
DDOx
Output Supply Current; NOTE 2 25 mA
NOTE 1: V
DDOx
denotes V
DDOA
, V
DDOB
, V
DDOC
, V
DDOD
, and V
DDOFB
.
NOTE 2: I
DDOx
denotes I
DDOA
, I
DDOB
, I
DDOC
, I
DDOD
, and I
DDOFB
.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDOx
+ 0.5V
Package Thermal Impedance, θ
JA
41.1°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8761I Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 25, 20166
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
DD
= V
DDA
= 3.3V±5%, V
DDOX
= 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input
High Voltage
OEA:OED, XTAL_SEL, MR, D_
SELAx, D_SELBx, FB_IN,
D_SELCx, D_SELDx, PLL_SEL,
FBDIV_SEL0, FBDIV_SEL1
2V
DD
+ 0.3 V
REF_CLK 2 V
DD
+ 0.3 V
V
IL
Input
Low Voltage
OEA:OED, XTAL_SEL, MR, D_
SELAx, D_SELBx, FB_IN,
D_SELCx, D_SELDx, PLL_SEL,
FBDIV_SEL0, FBDIV_SEL1
-0.3 0.8 V
REF_CLK -0.3 1.3 V
I
IH
Input
High Current
D_SELAx, D_SELBx, FB_IN, MR,
D_SELCx, D_SELDx, REF_CLK,
FBDIV_SEL1
V
DD
= V
IN
= 3.465V or
2.625V
150 µA
XTAL_SEL, PLL_SEL, FBDIV_
SEL0, OEA:OED
V
DD
= V
IN
= 3.465V or
2.625V
5µA
I
IL
Input
Low Current
D_SELAx, D_SELBx, FB_IN, MR,
D_SELCx, D_SELDx, REF_CLK,
FBDIV_SEL1
V
DD
= 3.465V or
2.625V, V
IN
= 0V
-5 µA
XTAL_SEL, PLL_SEL, FBDIV_
SEL0, OEA:OED
V
DD
= 3.465V or
2.625V, V
IN
= 0V
-150 µA
V
OH
Output High Voltage; NOTE 1
V
DDOx
= 3.465V 2.6 V
V
DDOx
= 2.625V 1.8
V
OL
Output Low Voltage; NOTE 1
V
DDOx
= 3.465V or
2.625V
0.5 V
I
OZL
Output Tristate Current Low -5 µA
I
OZH
Output Tristate Current High 5µA
NOTE 1: Outputs terminated with 50Ω to V
DDOx
/2. See Parameter Measurement Information section,
“Output Load Test Circuit”.
TABLE 5. CRYSTAL CHARACTERISTICS
TABLE 6. PLL INPUT REFERENCE CHARACTERISTICS, V
DD
= V
DDA
= V
DDOX
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
REF
Reference Frequency 12.5 83.33 MHz
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 10 38 MHz
Equivalent Series Resistance (ESR) 70 Ω
Shunt Capacitance 7 pF
Drive Level 1mW
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

8761CYILF

Mfr. #:
Buy 8761CYILF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 17 LVCMOS OUT CLOCK GEN
Lifecycle:
New from this manufacturer.
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