8761I Data Sheet
©2016 Integrated Device Technology, Inc Revision C January 25, 20167
TABLE 7A. AC CHARACTERISTICS, V
DD
= V
DDA
= V
DDOX
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 166.67 MHz
t(Ø) Static Phase Offset; NOTE 1, 7 f = 50MHz -150 150 ps
tsk(b) Bank Skew; NOTE 2, 6 50 ps
tsk(o) Output Skew; NOTE 3, 6 250 ps
tjit(cc) Cycle-to-Cycle Jitter; 6
f = 50MHz; NOTE 4, 7 70 ps
f = 25MHz XTAL,
133.3MHz out
190 ps
tjit(per) Period Jitter, RMS; NOTE 4, 6, 7, 8 17 ps
t
L
PLL Lock Time 1ms
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 250 800 ps
odc Output Duty Cycle; NOTE 5, 7 45 55 %
NOTE 1: Defi ned as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable. Measured from V
DD
/2 of the input to
V
DDOx
/2 of the output.
NOTE 2: Defi ned as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOx
/2.
NOTE 4: Jitter performance using LVCMOS inputs.
NOTE 5: Measured using REF_CLK. For XTAL input, refer to Application Note.
NOTE 6: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 7: Tested with D_SELXX =10 (divide by 6); FBDIV_SEL = 00 (divide by 6).
NOTE 8: This parameter is defi ned as an RMS value.
TABLE 7B. AC CHARACTERISTICS, V
DD
= V
DDA
= 3.3V±5%, V
DDOX
= 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 166.67 MHz
t(Ø) Static Phase Offset; NOTE 1, 7 f = 50MHz -350 20 ps
tsk(b) Bank Skew; NOTE 2, 6 50 ps
tsk(o) Output Skew; NOTE 3, 6 250 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 6
f = 50MHz; NOTE 4, 7 70 ps
f = 25MHz XTAL,
133.3MHz out
190 ps
tjit(per) Period Jitter, RMS; NOTE 4, 6, 7, 8 17 ps
t
L
PLL Lock Time 1ms
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 250 800 ps
odc Output Duty Cycle; NOTE 5, 7 45 55 %
NOTE 1: Defi ned as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable. Measured from V
DD
/2 of the input to
V
DDOX
/2 of the output.
NOTE 2: Defi ned as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
DDOx
/2.
NOTE 4: Jitter performance using LVCMOS inputs.
NOTE 5: Measured using REF_CLK. For XTAL input, refer to Application Note.
NOTE 6: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 7: Tested with D_SELXX =10 (divide by 6); FBDIV_SEL = 00 (divide by 6).
NOTE 8: This parameter is defi ned as an RMS value
