MT89L86 Data Sheet
16
Zarlink Semiconductor Inc.
Table 6 - Use of STA Bits for Identical I/O Data Rate Operation
* - for Data Memory Read operations A0 is not required since two nibbles are provided per read access.
Table 7 - Use of STA Bits for Different I/O Data Rate Operation
Note:In rate conversion applications, Data Memory subsections have different sizes than Connection Memory subsections. This
implies that different address inputs are used to select individual positions within the subsections for each type of memory.
Identical
I/O
Rate
# of Input x
Output
Streams
STA bits used to
select subsections
of the Data
Memory
STA bits used to
select subsections
of the Connection
Memory
Input Address pins used to
select individual Connection
and Data Memory positions
within the selected
subsection
2 Mb/s 8x8 STA2, STA1, STA0 STA2, STA1, STA0 A4, A3, A2, A1, A0
2 Mb/s 4x4 STA1, STA0 STA1, STA0 A4, A3, A2, A1, A0
2 Mb/s 16x8 STA3, STA2, STA1,
STA0
STA2, STA1, STA0 A4, A3, A2, A1, A0
4 Mb/s 4x4 STA1, STA0 STA1, STA0 A6, A4, A3, A2, A1, A0
4 Mb/s 8x4 STA2, STA1, STA0 STA1, STA0 A6, A4, A3, A2, A1, A0
8 Mb/s 2x2 STA0 STA0 A7, A6, A4, A3, A2, A1, A0
Nibble Switch
(2 Mb/s)
8x4 STA2, STA1, STA0 STA1, STA0 A6, A4, A3, A2, A1, A0 *
Different
I/O
Rate
Input x
Output
Streams
Config.
STA bits used
to select
Data
Memory
subsections
STA bits used
to select
Connection
Memory
subsections
Input Address pins used
to access individual
Data Memory
positions within the
selected subsection
Input Address pins used
to access individual
Connection Memory
positions within the
selected subsection
2 Mb/s to 4
Mb/s
8x4 STA2, STA1,
STA0
STA1, STA0 A4, A3, A2, A1, A0 A6,
A4, A3, A2, A1, A0
2 Mb/s to 8
Mb/s
8x2 STA2, STA1,
STA0
STA0 A4, A3, A2, A1, A0 A7, A6, A4, A3, A2, A1,
A0
4 Mb/s to 2
Mb/s
4x8 STA1, STA0 STA2, STA1,
STA0
A6,
A4, A3, A2, A1, A0 A4, A3, A2, A1, A0
8 Mb/s to 2
Mb/s
2x8 STA0 STA2, STA1,
STA0
A7, A6, A4, A3, A2, A1,
A0
A4, A3, A2, A1, A0
