MT89L86 Data Sheet
36
Zarlink Semiconductor Inc.
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
AC Electrical Characteristics
†
- Intel/National- HPC Multiplexed Bus Mode
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics Sym. Min. Typ.
‡
Max. Units Test Conditions
1 ALE pulse width t
ALW
20 ns
2 Address setup from ALE falling t
ADS
2ns
3 Address hold from ALE falling t
ADH
2ns
4RD
active after ALE falling t
ALRD
10 ns
5 Data setup from DTA
Low on Read t
DDR
0nsC
L
=150 pF
6CS
hold after RD/WR t
CSRW
0ns
7RD
pulse width (fast read) t
RW
80 ns
8CS
setup from RD t
CSR
0ns
9 Data hold after RD
t
DHR
10 50 90 ns C
L
=150 pF,R
L
=1 K
10 WR
pulse width (fast write) t
WW
90 ns
11 WR
delay after ALE falling t
ALWR
10 ns
12 CS
setup from WR t
CSW
0ns
13 Data setup from WR
(fast write)
t
DSW
90 ns
14 Valid Data Delay on write
(slow write)
t
SWD
122 ns
15 Data hold after WR
inactive t
DHW
5ns
16 Acknowledgment Delay:
Reading Data Memory
Reading/Writing Conn. Memories
Writing to Control & Mode Reg.
Reading from Control & Mode Reg.
t
AKD
560
62/30
25
52
1220
120/53
65
120
ns
ns
ns
ns
C
L
=150 pF
17 Acknowledgment Hold Time t
AKH
50 80 ns C
L
=150 pF,R
L
=1 K*
